/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
XCoreMachineFunctionInfo.cpp | 44 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); 46 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), 60 FPSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), 73 unsigned Size = TRI.getSpillSize(RC);
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XCoreFrameLowering.cpp | 585 unsigned Size = TRI.getSpillSize(RC);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
MipsMachineFunction.cpp | 63 EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), 78 TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false); 101 TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false);
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MipsFrameLowering.cpp | 128 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
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MipsSEFrameLowering.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
HexagonVExtract.cpp | 126 int FI = MFI.CreateSpillStackObject(HRI.getSpillSize(VecRC),
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HexagonFrameLowering.cpp | [all...] |
HexagonInstrInfo.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
ARCInstrInfo.cpp | 297 assert(TRI->getSpillSize(*RC) == 4 && 324 assert(TRI->getSpillSize(*RC) == 4 &&
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ARCFrameLowering.cpp | 423 RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
StackMaps.cpp | 164 Locs.emplace_back(Location::Register, TRI->getSpillSize(*RC), 250 unsigned Size = TRI->getSpillSize(*TRI->getMinimalPhysRegClass(Reg));
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TargetInstrInfo.cpp | 386 Size = TRI->getSpillSize(*RC); 403 assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range"); 406 Offset = TRI->getSpillSize(*RC) - (Offset + Size); [all...] |
VirtRegMap.cpp | 96 unsigned Size = TRI->getSpillSize(*RC);
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TargetLoweringBase.cpp | [all...] |
PrologEpilogInserter.cpp | 376 unsigned Size = RegInfo->getSpillSize(*RC); [all...] |
RegAllocFast.cpp | 240 unsigned Size = TRI->getSpillSize(RC); [all...] |
RegisterScavenging.cpp | 468 unsigned NeedSize = TRI->getSpillSize(RC);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
RISCVFrameLowering.cpp | 260 RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false);
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
TargetRegisterInfo.h | 320 unsigned getSpillSize(const TargetRegisterClass &RC) const { [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
SIFrameLowering.cpp | 731 TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
X86InstrInfo.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
AArch64FrameLowering.cpp | [all...] |
AArch64InstrInfo.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
ARMFrameLowering.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
PPCFrameLowering.cpp | [all...] |