1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef __SOC_ROCKCHIP_RK3399_GRF_H__ 7 #define __SOC_ROCKCHIP_RK3399_GRF_H__ 8 9 struct rk3399_grf_regs { 10 u32 reserved[0x800]; 11 u32 usb3_perf_con0; 12 u32 usb3_perf_con1; 13 u32 usb3_perf_con2; 14 u32 usb3_perf_rd_max_latency_num; 15 u32 usb3_perf_rd_latency_samp_num; 16 u32 usb3_perf_rd_latency_acc_num; 17 u32 usb3_perf_rd_axi_total_byte; 18 u32 usb3_perf_wr_axi_total_byte; 19 u32 usb3_perf_working_cnt; 20 u32 reserved1[0x103]; 21 u32 usb3otg0_con0; 22 u32 usb3otg0_con1; 23 u32 reserved2[2]; 24 u32 usb3otg1_con0; 25 u32 usb3otg1_con1; 26 u32 reserved3[2]; 27 u32 usb3otg0_status_lat0; 28 u32 usb3otg0_status_lat1; 29 u32 usb3otg0_status_cb; 30 u32 reserved4; 31 u32 usb3otg1_status_lat0; 32 u32 usb3otg1_status_lat1; 33 u32 usb3ogt1_status_cb; 34 u32 reserved5[0x6e5]; 35 u32 pcie_perf_con0; 36 u32 pcie_perf_con1; 37 u32 pcie_perf_con2; 38 u32 pcie_perf_rd_max_latency_num; 39 u32 pcie_perf_rd_latency_samp_num; 40 u32 pcie_perf_rd_laterncy_acc_num; 41 u32 pcie_perf_rd_axi_total_byte; 42 u32 pcie_perf_wr_axi_total_byte; 43 u32 pcie_perf_working_cnt; 44 u32 reserved6[0x37]; 45 u32 usb20_host0_con0; 46 u32 usb20_host0_con1; 47 u32 reserved7[2]; 48 u32 usb20_host1_con0; 49 u32 usb20_host1_con1; 50 u32 reserved8[2]; 51 u32 hsic_con0; 52 u32 hsic_con1; 53 u32 reserved9[6]; 54 u32 grf_usbhost0_status; 55 u32 grf_usbhost1_Status; 56 u32 grf_hsic_status; 57 u32 reserved10[0xc9]; 58 u32 hsicphy_con0; 59 u32 reserved11[3]; 60 u32 usbphy0_ctrl[26]; 61 u32 reserved12[6]; 62 u32 usbphy1[26]; 63 u32 reserved13[0x72f]; 64 u32 soc_con9; 65 u32 reserved14[0x0a]; 66 u32 soc_con20; 67 u32 soc_con21; 68 u32 soc_con22; 69 u32 soc_con23; 70 u32 soc_con24; 71 u32 soc_con25; 72 u32 soc_con26; 73 u32 reserved15[0xf65]; 74 u32 cpu_con[4]; 75 u32 reserved16[0x1c]; 76 u32 cpu_status[6]; 77 u32 reserved17[0x1a]; 78 u32 a53_perf_con[4]; 79 u32 a53_perf_rd_mon_st; 80 u32 a53_perf_rd_mon_end; 81 u32 a53_perf_wr_mon_st; 82 u32 a53_perf_wr_mon_end; 83 u32 a53_perf_rd_max_latency_num; 84 u32 a53_perf_rd_latency_samp_num; 85 u32 a53_perf_rd_laterncy_acc_num; 86 u32 a53_perf_rd_axi_total_byte; 87 u32 a53_perf_wr_axi_total_byte; 88 u32 a53_perf_working_cnt; 89 u32 a53_perf_int_status; 90 u32 reserved18[0x31]; 91 u32 a72_perf_con[4]; 92 u32 a72_perf_rd_mon_st; 93 u32 a72_perf_rd_mon_end; 94 u32 a72_perf_wr_mon_st; 95 u32 a72_perf_wr_mon_end; 96 u32 a72_perf_rd_max_latency_num; 97 u32 a72_perf_rd_latency_samp_num; 98 u32 a72_perf_rd_laterncy_acc_num; 99 u32 a72_perf_rd_axi_total_byte; 100 u32 a72_perf_wr_axi_total_byte; 101 u32 a72_perf_working_cnt; 102 u32 a72_perf_int_status; 103 u32 reserved19[0x7f6]; 104 u32 soc_con5; 105 u32 soc_con6; 106 u32 reserved20[0x779]; 107 u32 gpio2a_iomux; 108 union { 109 u32 iomux_spi2; 110 u32 gpio2b_iomux; 111 }; 112 union { 113 u32 gpio2c_iomux; 114 u32 iomux_spi5; 115 }; 116 u32 gpio2d_iomux; 117 union { 118 u32 gpio3a_iomux; 119 u32 iomux_spi0; 120 }; 121 u32 gpio3b_iomux; 122 u32 gpio3c_iomux; 123 union { 124 u32 iomux_i2s0; 125 u32 gpio3d_iomux; 126 }; 127 union { 128 u32 iomux_i2sclk; 129 u32 gpio4a_iomux; 130 }; 131 union { 132 u32 iomux_sdmmc; 133 u32 iomux_uart2a; 134 u32 gpio4b_iomux; 135 }; 136 union { 137 u32 iomux_pwm_0; 138 u32 iomux_pwm_1; 139 u32 iomux_uart2b; 140 u32 iomux_uart2c; 141 u32 iomux_edp_hotplug; 142 u32 gpio4c_iomux; 143 }; 144 u32 gpio4d_iomux; 145 u32 reserved21[4]; 146 u32 gpio2_p[4]; 147 u32 gpio3_p[4]; 148 u32 gpio4_p[4]; 149 u32 reserved22[4]; 150 u32 gpio2_sr[3][4]; 151 u32 reserved23[4]; 152 u32 gpio2_smt[3][4]; 153 u32 reserved24[(0xe100 - 0xe0ec)/4 - 1]; 154 u32 gpio2_e[4]; 155 u32 gpio3_e[7]; 156 u32 gpio4_e[5]; 157 u32 reserved24a[(0xe200 - 0xe13c)/4 - 1]; 158 u32 soc_con0; 159 u32 soc_con1; 160 u32 soc_con2; 161 u32 soc_con3; 162 u32 soc_con4; 163 u32 soc_con5_pcie; 164 u32 reserved25; 165 u32 soc_con7; 166 u32 soc_con8; 167 u32 soc_con9_pcie; 168 u32 reserved26[0x1e]; 169 u32 soc_status[6]; 170 u32 reserved27[0x32]; 171 u32 ddrc0_con0; 172 u32 ddrc0_con1; 173 u32 ddrc1_con0; 174 u32 ddrc1_con1; 175 u32 reserved28[0xac]; 176 u32 io_vsel; 177 u32 saradc_testbit; 178 u32 tsadc_testbit_l; 179 u32 tsadc_testbit_h; 180 u32 reserved29[0x6c]; 181 u32 chip_id_addr; 182 u32 reserved30[0x1f]; 183 u32 fast_boot_addr; 184 u32 reserved31[0x1df]; 185 u32 emmccore_con[12]; 186 u32 reserved32[4]; 187 u32 emmccore_status[4]; 188 u32 reserved33[0x1cc]; 189 u32 emmcphy_con[7]; 190 u32 reserved34; 191 u32 emmcphy_status; 192 }; 193 check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0); 194 195 struct rk3399_pmugrf_regs { 196 union { 197 u32 iomux_pwm_3a; 198 u32 gpio0a_iomux; 199 }; 200 u32 gpio0b_iomux; 201 u32 reserved0[2]; 202 union { 203 u32 spi1_rxd; 204 u32 tsadc_int; 205 u32 gpio1a_iomux; 206 }; 207 union { 208 u32 spi1_csclktx; 209 u32 iomux_pwm_3b; 210 u32 iomux_i2c0_sda; 211 u32 gpio1b_iomux; 212 }; 213 union { 214 u32 iomux_pwm_2; 215 u32 iomux_i2c0_scl; 216 u32 gpio1c_iomux; 217 }; 218 u32 gpio1d_iomux; 219 u32 reserved1[8]; 220 u32 gpio0_p[2]; 221 u32 reserved2[2]; 222 u32 gpio1_p[4]; 223 u32 reserved3[8]; 224 u32 gpio0a_e; 225 u32 reserved4; 226 u32 gpio0b_e; 227 u32 reserved5[5]; 228 u32 gpio1a_e; 229 u32 reserved6; 230 u32 gpio1b_e; 231 u32 reserved7; 232 u32 gpio1c_e; 233 u32 reserved8; 234 u32 gpio1d_e; 235 u32 reserved9[0x11]; 236 u32 gpio0l_sr; 237 u32 reserved10; 238 u32 gpio1l_sr; 239 u32 gpio1h_sr; 240 u32 reserved11[4]; 241 u32 gpio0a_smt; 242 u32 gpio0b_smt; 243 u32 reserved12[2]; 244 u32 gpio1a_smt; 245 u32 gpio1b_smt; 246 u32 gpio1c_smt; 247 u32 gpio1d_smt; 248 u32 reserved13[8]; 249 u32 gpio0l_he; 250 u32 reserved14; 251 u32 gpio1l_he; 252 u32 gpio1h_he; 253 u32 reserved15[4]; 254 u32 soc_con0; 255 u32 reserved16[9]; 256 u32 soc_con10; 257 u32 soc_con11; 258 u32 reserved17[0x24]; 259 u32 pmupvtm_con0; 260 u32 pmupvtm_con1; 261 u32 pmupvtm_status0; 262 u32 pmupvtm_status1; 263 u32 grf_osc_e; 264 u32 reserved18[0x2b]; 265 u32 os_reg0; 266 u32 os_reg1; 267 u32 os_reg2; 268 u32 os_reg3; 269 }; 270 check_member(rk3399_pmugrf_regs, os_reg3, 0x30c); 271 272 struct rk3399_pmusgrf_regs { 273 u32 ddr_rgn_con[35]; 274 u32 reserved[0x1fe5]; 275 u32 soc_con8; 276 u32 soc_con9; 277 u32 soc_con10; 278 u32 soc_con11; 279 u32 soc_con12; 280 u32 soc_con13; 281 u32 soc_con14; 282 u32 soc_con15; 283 u32 reserved1[3]; 284 u32 soc_con19; 285 u32 soc_con20; 286 u32 soc_con21; 287 u32 soc_con22; 288 u32 reserved2[0x29]; 289 u32 perilp_con[9]; 290 u32 reserved4[7]; 291 u32 perilp_status; 292 u32 reserved5[0xfaf]; 293 u32 soc_con0; 294 u32 soc_con1; 295 u32 reserved6[0x3e]; 296 u32 pmu_con[9]; 297 u32 reserved7[0x17]; 298 u32 fast_boot_addr; 299 u32 reserved8[0x1f]; 300 u32 efuse_prg_mask; 301 u32 efuse_read_mask; 302 u32 reserved9[0x0e]; 303 u32 pmu_slv_con0; 304 u32 pmu_slv_con1; 305 u32 reserved10[0x771]; 306 u32 soc_con3; 307 u32 soc_con4; 308 u32 soc_con5; 309 u32 soc_con6; 310 u32 soc_con7; 311 u32 reserved11[8]; 312 u32 soc_con16; 313 u32 soc_con17; 314 u32 soc_con18; 315 u32 reserved12[0xdd]; 316 u32 slv_secure_con0; 317 u32 slv_secure_con1; 318 u32 reserved13; 319 u32 slv_secure_con2; 320 u32 slv_secure_con3; 321 u32 slv_secure_con4; 322 }; 323 check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4); 324 325 enum { 326 /* GRF_GPIO2A_IOMUX */ 327 GRF_GPIO2A0_SEL_SHIFT = 0, 328 GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT, 329 GRF_I2C2_SDA = 2, 330 GRF_GPIO2A1_SEL_SHIFT = 2, 331 GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT, 332 GRF_I2C2_SCL = 2, 333 GRF_GPIO2A7_SEL_SHIFT = 14, 334 GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT, 335 GRF_I2C7_SDA = 2, 336 337 /* GRF_GPIO2B_IOMUX */ 338 GRF_GPIO2B0_SEL_SHIFT = 0, 339 GRF_GPIO2B0_SEL_MASK = 3 << GRF_GPIO2B0_SEL_SHIFT, 340 GRF_I2C7_SCL = 2, 341 GRF_GPIO2B1_SEL_SHIFT = 2, 342 GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT, 343 GRF_SPI2TPM_RXD = 1, 344 GRF_I2C6_SDA = 2, 345 GRF_GPIO2B2_SEL_SHIFT = 4, 346 GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT, 347 GRF_SPI2TPM_TXD = 1, 348 GRF_I2C6_SCL = 2, 349 GRF_GPIO2B3_SEL_SHIFT = 6, 350 GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT, 351 GRF_SPI2TPM_CLK = 1, 352 GRF_GPIO2B4_SEL_SHIFT = 8, 353 GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT, 354 GRF_SPI2TPM_CSN0 = 1, 355 356 /* GRF_GPIO2C_IOMUX */ 357 GRF_GPIO2C0_SEL_SHIFT = 0, 358 GRF_GPIO2C0_SEL_MASK = 3 << GRF_GPIO2C0_SEL_SHIFT, 359 GRF_UART0BT_SIN = 1, 360 GRF_GPIO2C1_SEL_SHIFT = 2, 361 GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT, 362 GRF_UART0BT_SOUT = 1, 363 GRF_GPIO2C4_SEL_SHIFT = 8, 364 GRF_GPIO2C4_SEL_MASK = 3 << GRF_GPIO2C4_SEL_SHIFT, 365 GRF_SPI5EXPPLUS_RXD = 2, 366 GRF_GPIO2C5_SEL_SHIFT = 10, 367 GRF_GPIO2C5_SEL_MASK = 3 << GRF_GPIO2C5_SEL_SHIFT, 368 GRF_SPI5EXPPLUS_TXD = 2, 369 GRF_GPIO2C6_SEL_SHIFT = 12, 370 GRF_GPIO2C6_SEL_MASK = 3 << GRF_GPIO2C6_SEL_SHIFT, 371 GRF_SPI5EXPPLUS_CLK = 2, 372 GRF_GPIO2C7_SEL_SHIFT = 14, 373 GRF_GPIO2C7_SEL_MASK = 3 << GRF_GPIO2C7_SEL_SHIFT, 374 GRF_SPI5EXPPLUS_CSN0 = 2, 375 376 /* GRF_GPIO3A_IOMUX */ 377 GRF_GPIO3A0_SEL_SHIFT = 0, 378 GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT, 379 GRF_MAC_TXD2 = 1, 380 GRF_GPIO3A1_SEL_SHIFT = 2, 381 GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT, 382 GRF_MAC_TXD3 = 1, 383 GRF_GPIO3A2_SEL_SHIFT = 4, 384 GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT, 385 GRF_MAC_RXD2 = 1, 386 GRF_GPIO3A3_SEL_SHIFT = 6, 387 GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT, 388 GRF_MAC_RXD3 = 1, 389 GRF_GPIO3A4_SEL_SHIFT = 8, 390 GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT, 391 GRF_MAC_TXD0 = 1, 392 GRF_SPI0NORCODEC_RXD = 2, 393 GRF_GPIO3A5_SEL_SHIFT = 10, 394 GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT, 395 GRF_MAC_TXD1 = 1, 396 GRF_SPI0NORCODEC_TXD = 2, 397 GRF_GPIO3A6_SEL_SHIFT = 12, 398 GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT, 399 GRF_MAC_RXD0 = 1, 400 GRF_SPI0NORCODEC_CLK = 2, 401 GRF_GPIO3A7_SEL_SHIFT = 14, 402 GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT, 403 GRF_MAC_RXD1 = 1, 404 GRF_SPI0NORCODEC_CSN0 = 2, 405 406 /* GRF_GPIO3B_IOMUX */ 407 GRF_GPIO3B0_SEL_SHIFT = 0, 408 GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT, 409 GRF_MAC_MDC = 1, 410 GRF_SPI0NORCODEC_CSN1 = 2, 411 GRF_GPIO3B1_SEL_SHIFT = 2, 412 GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT, 413 GRF_MAC_RXDV = 1, 414 GRF_GPIO3B3_SEL_SHIFT = 6, 415 GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT, 416 GRF_MAC_CLK = 1, 417 GRF_GPIO3B4_SEL_SHIFT = 8, 418 GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT, 419 GRF_MAC_TXEN = 1, 420 GRF_GPIO3B5_SEL_SHIFT = 10, 421 GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT, 422 GRF_MAC_MDIO = 1, 423 GRF_GPIO3B6_SEL_SHIFT = 12, 424 GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT, 425 GRF_MAC_RXCLK = 1, 426 427 /* GRF_GPIO3C_IOMUX */ 428 GRF_GPIO3C1_SEL_SHIFT = 2, 429 GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT, 430 GRF_MAC_TXCLK = 1, 431 432 /* GRF_GPIO4A_IOMUX */ 433 GRF_GPIO4A1_SEL_SHIFT = 2, 434 GRF_GPIO4A1_SEL_MASK = 3 << GRF_GPIO4A1_SEL_SHIFT, 435 GRF_I2C1_SDA = 1, 436 GRF_GPIO4A2_SEL_SHIFT = 4, 437 GRF_GPIO4A2_SEL_MASK = 3 << GRF_GPIO4A2_SEL_SHIFT, 438 GRF_I2C1_SCL = 1, 439 440 /* GRF_GPIO4B_IOMUX */ 441 GRF_GPIO4B0_SEL_SHIFT = 0, 442 GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT, 443 GRF_SDMMC_DATA0 = 1, 444 GRF_UART2DBGA_SIN = 2, 445 GRF_GPIO4B1_SEL_SHIFT = 2, 446 GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT, 447 GRF_SDMMC_DATA1 = 1, 448 GRF_UART2DBGA_SOUT = 2, 449 GRF_GPIO4B2_SEL_SHIFT = 4, 450 GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT, 451 GRF_SDMMC_DATA2 = 1, 452 GRF_GPIO4B3_SEL_SHIFT = 6, 453 GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT, 454 GRF_SDMMC_DATA3 = 1, 455 GRF_GPIO4B4_SEL_SHIFT = 8, 456 GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT, 457 GRF_SDMMC_CLKOUT = 1, 458 GRF_GPIO4B5_SEL_SHIFT = 10, 459 GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT, 460 GRF_SDMMC_CMD = 1, 461 462 /* GRF_GPIO4C_IOMUX */ 463 GRF_GPIO4C0_SEL_SHIFT = 0, 464 GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT, 465 GRF_UART2DGBB_SIN = 2, 466 GRF_HDMII2C_SCL = 3, 467 GRF_GPIO4C1_SEL_SHIFT = 2, 468 GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT, 469 GRF_UART2DGBB_SOUT = 2, 470 GRF_HDMII2C_SDA = 3, 471 GRF_GPIO4C2_SEL_SHIFT = 4, 472 GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT, 473 GRF_PWM_0 = 1, 474 GRF_GPIO4C3_SEL_SHIFT = 6, 475 GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT, 476 GRF_UART2DGBC_SIN = 1, 477 GRF_GPIO4C4_SEL_SHIFT = 8, 478 GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT, 479 GRF_UART2DBGC_SOUT = 1, 480 GRF_GPIO4C6_SEL_SHIFT = 12, 481 GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT, 482 GRF_PWM_1 = 1, 483 484 /* GRF_GPIO3A_E01 */ 485 GRF_GPIO3A0_E_SHIFT = 0, 486 GRF_GPIO3A0_E_MASK = 7 << GRF_GPIO3A0_E_SHIFT, 487 GRF_GPIO3A1_E_SHIFT = 3, 488 GRF_GPIO3A1_E_MASK = 7 << GRF_GPIO3A1_E_SHIFT, 489 GRF_GPIO3A2_E_SHIFT = 6, 490 GRF_GPIO3A2_E_MASK = 7 << GRF_GPIO3A2_E_SHIFT, 491 GRF_GPIO3A3_E_SHIFT = 9, 492 GRF_GPIO3A3_E_MASK = 7 << GRF_GPIO3A3_E_SHIFT, 493 GRF_GPIO3A4_E_SHIFT = 12, 494 GRF_GPIO3A4_E_MASK = 7 << GRF_GPIO3A4_E_SHIFT, 495 GRF_GPIO3A5_E0_SHIFT = 15, 496 GRF_GPIO3A5_E0_MASK = 1 << GRF_GPIO3A5_E0_SHIFT, 497 498 /* GRF_GPIO3A_E2 */ 499 GRF_GPIO3A5_E12_SHIFT = 0, 500 GRF_GPIO3A5_E12_MASK = 3 << GRF_GPIO3A5_E12_SHIFT, 501 GRF_GPIO3A6_E_SHIFT = 2, 502 GRF_GPIO3A6_E_MASK = 7 << GRF_GPIO3A6_E_SHIFT, 503 GRF_GPIO3A7_E_SHIFT = 5, 504 GRF_GPIO3A7_E_MASK = 7 << GRF_GPIO3A7_E_SHIFT, 505 506 /* GRF_GPIO3B_E01 */ 507 GRF_GPIO3B0_E_SHIFT = 0, 508 GRF_GPIO3B0_E_MASK = 7 << GRF_GPIO3B0_E_SHIFT, 509 GRF_GPIO3B1_E_SHIFT = 3, 510 GRF_GPIO3B1_E_MASK = 7 << GRF_GPIO3B1_E_SHIFT, 511 GRF_GPIO3B2_E_SHIFT = 6, 512 GRF_GPIO3B2_E_MASK = 7 << GRF_GPIO3B2_E_SHIFT, 513 GRF_GPIO3B3_E_SHIFT = 9, 514 GRF_GPIO3B3_E_MASK = 7 << GRF_GPIO3B3_E_SHIFT, 515 GRF_GPIO3B4_E_SHIFT = 12, 516 GRF_GPIO3B4_E_MASK = 7 << GRF_GPIO3B4_E_SHIFT, 517 GRF_GPIO3B5_E0_SHIFT = 15, 518 GRF_GPIO3B5_E0_MASK = 1 << GRF_GPIO3B5_E0_SHIFT, 519 520 /* GRF_GPIO3A_E2 */ 521 GRF_GPIO3B5_E12_SHIFT = 0, 522 GRF_GPIO3B5_E12_MASK = 3 << GRF_GPIO3B5_E12_SHIFT, 523 GRF_GPIO3B6_E_SHIFT = 2, 524 GRF_GPIO3B6_E_MASK = 7 << GRF_GPIO3B6_E_SHIFT, 525 GRF_GPIO3B7_E_SHIFT = 5, 526 GRF_GPIO3B7_E_MASK = 7 << GRF_GPIO3B7_E_SHIFT, 527 528 /* GRF_GPIO3C_E01 */ 529 GRF_GPIO3C0_E_SHIFT = 0, 530 GRF_GPIO3C0_E_MASK = 7 << GRF_GPIO3C0_E_SHIFT, 531 GRF_GPIO3C1_E_SHIFT = 3, 532 GRF_GPIO3C1_E_MASK = 7 << GRF_GPIO3C1_E_SHIFT, 533 GRF_GPIO3C2_E_SHIFT = 6, 534 GRF_GPIO3C2_E_MASK = 7 << GRF_GPIO3C2_E_SHIFT, 535 GRF_GPIO3C3_E_SHIFT = 9, 536 GRF_GPIO3C3_E_MASK = 7 << GRF_GPIO3C3_E_SHIFT, 537 GRF_GPIO3C4_E_SHIFT = 12, 538 GRF_GPIO3C4_E_MASK = 7 << GRF_GPIO3C4_E_SHIFT, 539 GRF_GPIO3C5_E0_SHIFT = 15, 540 GRF_GPIO3C5_E0_MASK = 1 << GRF_GPIO3C5_E0_SHIFT, 541 542 /* GRF_GPIO3C_E2 */ 543 GRF_GPIO3C5_E12_SHIFT = 0, 544 GRF_GPIO3C5_E12_MASK = 3 << GRF_GPIO3C5_E12_SHIFT, 545 GRF_GPIO3C6_E_SHIFT = 2, 546 GRF_GPIO3C6_E_MASK = 7 << GRF_GPIO3C6_E_SHIFT, 547 GRF_GPIO3C7_E_SHIFT = 5, 548 GRF_GPIO3C7_E_MASK = 7 << GRF_GPIO3C7_E_SHIFT, 549 550 /* GRF_SOC_CON7 */ 551 GRF_UART_DBG_SEL_SHIFT = 10, 552 GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, 553 GRF_UART_DBG_SEL_C = 2, 554 555 /* GRF_SOC_CON20 */ 556 GRF_DSI0_VOP_SEL_SHIFT = 0, 557 GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT, 558 GRF_DSI0_VOP_SEL_B = 0, 559 GRF_DSI0_VOP_SEL_L = 1, 560 GRF_RK3399_HDMI_VOP_SEL_MASK = 1 << 6, 561 GRF_RK3399_HDMI_VOP_SEL_B = 0 << 6, 562 GRF_RK3399_HDMI_VOP_SEL_L = 1 << 6, 563 564 /* GRF_SOC_CON22 */ 565 GRF_DPHY_TX0_RXMODE_SHIFT = 0, 566 GRF_DPHY_TX0_RXMODE_MASK = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT, 567 GRF_DPHY_TX0_RXMODE_EN = 0xb, 568 GRF_DPHY_TX0_RXMODE_DIS = 0, 569 570 GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4, 571 GRF_DPHY_TX0_TXSTOPMODE_MASK = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT, 572 GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc, 573 GRF_DPHY_TX0_TXSTOPMODE_DIS = 0, 574 575 GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12, 576 GRF_DPHY_TX0_TURNREQUEST_MASK = 577 0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT, 578 GRF_DPHY_TX0_TURNREQUEST_EN = 0x1, 579 GRF_DPHY_TX0_TURNREQUEST_DIS = 0, 580 581 /* PMUGRF_GPIO0A_IOMUX */ 582 PMUGRF_GPIO0A6_SEL_SHIFT = 12, 583 PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT, 584 PMUGRF_PWM_3A = 1, 585 586 /* PMUGRF_GPIO1A_IOMUX */ 587 PMUGRF_GPIO1A7_SEL_SHIFT = 14, 588 PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT, 589 PMUGRF_SPI1EC_RXD = 2, 590 591 /* PMUGRF_GPIO1B_IOMUX */ 592 PMUGRF_GPIO1B0_SEL_SHIFT = 0, 593 PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT, 594 PMUGRF_SPI1EC_TXD = 2, 595 PMUGRF_GPIO1B1_SEL_SHIFT = 2, 596 PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT, 597 PMUGRF_SPI1EC_CLK = 2, 598 PMUGRF_GPIO1B2_SEL_SHIFT = 4, 599 PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT, 600 PMUGRF_SPI1EC_CSN0 = 2, 601 PMUGRF_GPIO1B3_SEL_SHIFT = 6, 602 PMUGRF_GPIO1B3_SEL_MASK = 3 << PMUGRF_GPIO1B3_SEL_SHIFT, 603 PMUGRF_I2C4_SDA = 1, 604 PMUGRF_GPIO1B4_SEL_SHIFT = 8, 605 PMUGRF_GPIO1B4_SEL_MASK = 3 << PMUGRF_GPIO1B4_SEL_SHIFT, 606 PMUGRF_I2C4_SCL = 1, 607 PMUGRF_GPIO1B6_SEL_SHIFT = 12, 608 PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT, 609 PMUGRF_PWM_3B = 1, 610 PMUGRF_GPIO1B7_SEL_SHIFT = 14, 611 PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT, 612 PMUGRF_I2C0PMU_SDA = 2, 613 614 /* PMUGRF_GPIO1C_IOMUX */ 615 PMUGRF_GPIO1C0_SEL_SHIFT = 0, 616 PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT, 617 PMUGRF_I2C0PMU_SCL = 2, 618 PMUGRF_GPIO1C3_SEL_SHIFT = 6, 619 PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT, 620 PMUGRF_PWM_2 = 1, 621 PMUGRF_GPIO1C4_SEL_SHIFT = 8, 622 PMUGRF_GPIO1C4_SEL_MASK = 3 << PMUGRF_GPIO1C4_SEL_SHIFT, 623 PMUGRF_I2C8PMU_SDA = 1, 624 PMUGRF_GPIO1C5_SEL_SHIFT = 10, 625 PMUGRF_GPIO1C5_SEL_MASK = 3 << PMUGRF_GPIO1C5_SEL_SHIFT, 626 PMUGRF_I2C8PMU_SCL = 1, 627 }; 628 629 /* GRF_SOC_CON5 */ 630 enum { 631 RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9, 632 RK3399_GMAC_PHY_INTF_SEL_MASK = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), 633 RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), 634 RK3399_GMAC_PHY_INTF_SEL_RMII = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), 635 636 RK3399_GMAC_CLK_SEL_SHIFT = 4, 637 RK3399_GMAC_CLK_SEL_MASK = (3 << RK3399_GMAC_CLK_SEL_SHIFT), 638 RK3399_GMAC_CLK_SEL_125M = (0 << RK3399_GMAC_CLK_SEL_SHIFT), 639 RK3399_GMAC_CLK_SEL_25M = (3 << RK3399_GMAC_CLK_SEL_SHIFT), 640 RK3399_GMAC_CLK_SEL_2_5M = (2 << RK3399_GMAC_CLK_SEL_SHIFT), 641 }; 642 643 /* GRF_SOC_CON6 */ 644 enum { 645 RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15, 646 RK3399_RXCLK_DLY_ENA_GMAC_MASK = 647 (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT), 648 RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 649 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE = 650 (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT), 651 652 RK3399_TXCLK_DLY_ENA_GMAC_SHIFT = 7, 653 RK3399_TXCLK_DLY_ENA_GMAC_MASK = 654 (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT), 655 RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 656 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE = 657 (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT), 658 659 RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 660 RK3399_CLK_RX_DL_CFG_GMAC_MASK = 661 (0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT), 662 663 RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 664 RK3399_CLK_TX_DL_CFG_GMAC_MASK = 665 (0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT), 666 }; 667 668 #endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */ 669
