| /external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/BtVer2/ |
| clear-super-register-1.s | 9 lzcnt %ecx, %eax label
11 ## The AND can start immediately after the LZCNT.
|
| partial-reg-update-6.s | 5 # Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the
7 # The last lzcnt has a false dependency on %cx. However, even in this case, the
11 lzcnt (%rsp), %cx label
12 lzcnt 2(%rsp), %cx label
|
| partial-reg-update-4.s | 6 # The lzcnt cannot execute in parallel with the imul because there is a false
10 lzcnt %ax, %bx label
|
| partial-reg-update-2.s | 5 lzcnt %ax, %bx label
|
| partial-reg-update-5.s | 6 lzcnt %ax, %bx ## partial register stall. label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/Znver1/ |
| partial-reg-update-6.s | 4 # Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the
6 # The last lzcnt has a false dependency on %cx. However, even in this case, the
10 lzcnt (%rsp), %cx label
11 lzcnt 2(%rsp), %cx label
|
| partial-reg-update-2.s | 5 lzcnt %ax, %bx label
|
| partial-reg-update-4.s | 4 # The lzcnt cannot execute in parallel with the imul because there is a false
8 lzcnt %ax, %bx label
|
| partial-reg-update-5.s | 4 lzcnt %ax, %bx ## partial register stall. label
|
| /external/v8/src/ia32/ |
| assembler-ia32.h | 1534 void lzcnt(Register dst, Register src) { lzcnt(dst, Operand(src)); } function in class:v8::internal::Assembler
[all...] |
| macro-assembler-ia32.cc | [all...] |
| assembler-ia32.cc | 148 if (cpu.has_lzcnt() && FLAG_enable_lzcnt) supported_ |= 1u << LZCNT;
161 "SSE3=%d SSSE3=%d SSE4_1=%d AVX=%d FMA3=%d BMI1=%d BMI2=%d LZCNT=%d "
166 CpuFeatures::IsSupported(BMI2), CpuFeatures::IsSupported(LZCNT),
3067 void Assembler::lzcnt(Register dst, Operand src) { function in class:v8::internal::Assembler
[all...] |
