1 /* 2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __MT8173_DEF_H__ 8 #define __MT8173_DEF_H__ 9 10 #if RESET_TO_BL31 11 #error "MT8173 is incompatible with RESET_TO_BL31!" 12 #endif 13 14 #define MT8173_PRIMARY_CPU 0x0 15 16 /* Register base address */ 17 #define IO_PHYS (0x10000000) 18 #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) 19 #define SRAMROM_SEC_BASE (IO_PHYS + 0x1800) 20 #define PERI_CON_BASE (IO_PHYS + 0x3000) 21 #define GPIO_BASE (IO_PHYS + 0x5000) 22 #define SPM_BASE (IO_PHYS + 0x6000) 23 #define RGU_BASE (IO_PHYS + 0x7000) 24 #define PMIC_WRAP_BASE (IO_PHYS + 0xD000) 25 #define DEVAPC0_BASE (IO_PHYS + 0xE000) 26 #define MCUCFG_BASE (IO_PHYS + 0x200000) 27 #define APMIXED_BASE (IO_PHYS + 0x209000) 28 #define TRNG_BASE (IO_PHYS + 0x20F000) 29 #define CRYPT_BASE (IO_PHYS + 0x210000) 30 #define MT_GIC_BASE (IO_PHYS + 0x220000) 31 #define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000) 32 33 /* Aggregate of all devices in the first GB */ 34 #define MTK_DEV_RNG0_BASE IO_PHYS 35 #define MTK_DEV_RNG0_SIZE 0x400000 36 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 37 #define MTK_DEV_RNG1_SIZE 0x4000000 38 39 /* SRAMROM related registers */ 40 #define SRAMROM_SEC_CTRL (SRAMROM_SEC_BASE + 0x4) 41 #define SRAMROM_SEC_ADDR (SRAMROM_SEC_BASE + 0x8) 42 43 /* DEVAPC0 related registers */ 44 #define DEVAPC0_MAS_SEC_0 (DEVAPC0_BASE + 0x500) 45 #define DEVAPC0_APC_CON (DEVAPC0_BASE + 0xF00) 46 47 /******************************************************************************* 48 * UART related constants 49 ******************************************************************************/ 50 #define MT8173_UART0_BASE (IO_PHYS + 0x01002000) 51 #define MT8173_UART1_BASE (IO_PHYS + 0x01003000) 52 #define MT8173_UART2_BASE (IO_PHYS + 0x01004000) 53 #define MT8173_UART3_BASE (IO_PHYS + 0x01005000) 54 55 #define MT8173_BAUDRATE (115200) 56 #define MT8173_UART_CLOCK (26000000) 57 58 /******************************************************************************* 59 * System counter frequency related constants 60 ******************************************************************************/ 61 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 62 63 /******************************************************************************* 64 * GIC-400 & interrupt handling related constants 65 ******************************************************************************/ 66 67 /* Base MTK_platform compatible GIC memory map */ 68 #define BASE_GICD_BASE (MT_GIC_BASE + 0x1000) 69 #define BASE_GICC_BASE (MT_GIC_BASE + 0x2000) 70 #define BASE_GICR_BASE 0 /* no GICR in GIC-400 */ 71 #define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) 72 #define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) 73 #define INT_POL_CTL0 0x10200620 74 75 #define GIC_PRIVATE_SIGNALS (32) 76 77 /******************************************************************************* 78 * CCI-400 related constants 79 ******************************************************************************/ 80 #define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 81 #define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 82 83 /******************************************************************************* 84 * WDT related constants 85 ******************************************************************************/ 86 #define MTK_WDT_BASE (RGU_BASE + 0) 87 #define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014) 88 89 #define MTK_WDT_MODE_DUAL_MODE 0x0040 90 #define MTK_WDT_MODE_IRQ 0x0008 91 #define MTK_WDT_MODE_KEY 0x22000000 92 #define MTK_WDT_MODE_EXTEN 0x0004 93 #define MTK_WDT_SWRST_KEY 0x1209 94 95 /* FIQ platform related define */ 96 #define MT_IRQ_SEC_SGI_0 8 97 #define MT_IRQ_SEC_SGI_1 9 98 #define MT_IRQ_SEC_SGI_2 10 99 #define MT_IRQ_SEC_SGI_3 11 100 #define MT_IRQ_SEC_SGI_4 12 101 #define MT_IRQ_SEC_SGI_5 13 102 #define MT_IRQ_SEC_SGI_6 14 103 #define MT_IRQ_SEC_SGI_7 15 104 105 /* 106 * Macros for local power states in MTK platforms encoded by State-ID field 107 * within the power-state parameter. 108 */ 109 /* Local power state for power domains in Run state. */ 110 #define MTK_LOCAL_STATE_RUN 0 111 /* Local power state for retention. Valid only for CPU power domains */ 112 #define MTK_LOCAL_STATE_RET 1 113 /* Local power state for OFF/power-down. Valid for CPU and cluster power 114 * domains 115 */ 116 #define MTK_LOCAL_STATE_OFF 2 117 118 #if PSCI_EXTENDED_STATE_ID 119 /* 120 * Macros used to parse state information from State-ID if it is using the 121 * recommended encoding for State-ID. 122 */ 123 #define MTK_LOCAL_PSTATE_WIDTH 4 124 #define MTK_LOCAL_PSTATE_MASK ((1 << MTK_LOCAL_PSTATE_WIDTH) - 1) 125 126 /* Macros to construct the composite power state */ 127 128 /* Make composite power state parameter till power level 0 */ 129 130 #define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 131 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 132 #else 133 #define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 134 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 135 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 136 ((type) << PSTATE_TYPE_SHIFT)) 137 138 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 139 140 /* Make composite power state parameter till power level 1 */ 141 #define mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 142 (((lvl1_state) << MTK_LOCAL_PSTATE_WIDTH) | \ 143 mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 144 145 /* Make composite power state parameter till power level 2 */ 146 #define mtk_make_pwrstate_lvl2( \ 147 lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 148 (((lvl2_state) << (MTK_LOCAL_PSTATE_WIDTH * 2)) | \ 149 mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 150 151 152 #endif /* __MT8173_DEF_H__ */ 153
