| /device/linaro/bootloader/arm-trusted-firmware/include/common/aarch32/ |
| asm_macros.S | 18 .macro ldcopr reg, coproc, opc1, CRn, CRm, opc2
19 mrc \coproc, \opc1, \reg, \CRn, \CRm, \opc2
22 .macro ldcopr16 reg1, reg2, coproc, opc1, CRm
23 mrrc \coproc, \opc1, \reg1, \reg2, \CRm
26 .macro stcopr reg, coproc, opc1, CRn, CRm, opc2
27 mcr \coproc, \opc1, \reg, \CRn, \CRm, \opc2
30 .macro stcopr16 reg1, reg2, coproc, opc1, CRm
31 mcrr \coproc, \opc1, \reg1, \reg2, \CRm
|
| /device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch32/ |
| arch_helpers.h | 19 #define _DEFINE_COPROCR_WRITE_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
22 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
25 #define _DEFINE_COPROCR_READ_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
29 __asm__ volatile ("mrc "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : "=r" (v));\
43 #define _DEFINE_COPROCR_WRITE_FUNC_64(_name, coproc, opc1, CRm) \
46 __asm__ volatile ("mcrr "#coproc","#opc1", %Q0, %R0,"#CRm : : "r" (v));\
49 #define _DEFINE_COPROCR_READ_FUNC_64(_name, coproc, opc1, CRm) \
52 __asm__ volatile ("mrrc "#coproc","#opc1", %Q0, %R0,"#CRm : "=r" (v));\
108 #define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
112 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/lib/aarch32/ |
| cache_helpers.S | 22 .macro do_dcache_maintenance_by_mva op, coproc, opc1, CRn, CRm, opc2
31 stcopr r0, \coproc, \opc1, \CRn, \CRm, \opc2
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ThumbDisassembler.c | 263 { "CPD", 0xee000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
264 { "CPD2", 0xfe000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
266 { "MRC", 0xee100000, 0xff100000, MRC_THUMB2 }, // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
267 { "MRC2", 0xfe100000, 0xff100000, MRC_THUMB2 }, // MRC2 <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
268 { "MRRC", 0xec500000, 0xfff00000, MRRC_THUMB2 }, // MRRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
269 { "MRRC2", 0xfc500000, 0xfff00000, MRRC_THUMB2 }, // MRR2 <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
500 UINT32 coproc, opc1, opc2, CRd, CRn, CRm;
local
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| nv50_ir_emit_gk110.cpp | 48 void emitForm_21(const Instruction *, uint32_t opc2, uint32_t opc1);
422 uint32_t opc1)
432 code[1] = opc1 << 20;
1844 uint64_t opc1, opc2; local
[all...] |
| /external/capstone/arch/ARM/ |
| ARMDisassembler.c | 5096 unsigned opc1 = fieldFromInstruction_4(Val, 4, 4); local
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 5274 unsigned opc1 = fieldFromInstruction(Val, 4, 4); local
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 5297 unsigned opc1 = fieldFromInstruction(Val, 4, 4); local
[all...] |
| /external/v8/src/arm/ |
| simulator-arm.cc | 3526 int opc1 = instr->Bits(23, 21); local
[all...] |
