/art/tools/dexanalyze/ |
dexanalyze_bytecode.cc | 266 uint32_t out_reg = inst->VRegA_22c(); local 274 ExtendPrefix(&out_reg, &field_idx); 275 CHECK(InstNibbles(new_opcode, {out_reg, field_idx})); 286 CHECK(InstNibbles(new_opcode, {out_reg, receiver, type_idx, field_idx})); 296 uint32_t out_reg = is_jumbo ? inst->VRegA_31c() : inst->VRegA_21c(); local 303 ExtendPrefix(&out_reg, &idx); 304 CHECK(InstNibbles(opcode, {out_reg, idx})); 324 uint32_t out_reg = inst->VRegA_21c(); local 334 ExtendPrefix(&out_reg, &field_idx); 335 if (InstNibbles(new_opcode, {out_reg, field_idx})) 440 uint32_t out_reg = inst->VRegA_22c(); local 454 uint32_t out_reg = inst->VRegA_22c(); local 469 uint32_t out_reg = inst->VRegA_21c(); local [all...] |
/art/compiler/jni/quick/ |
jni_compiler.cc | 351 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); local 352 __ CreateHandleScopeEntry(out_reg, class_handle_scope_offset, 398 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); local 399 __ CreateHandleScopeEntry(out_reg, locked_object_handle_scope_offset, 473 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); local 474 __ CreateHandleScopeEntry(out_reg, handle_scope_offset, 593 ManagedRegister out_reg = end_jni_conv->CurrentParamRegister(); local 594 __ Load(out_reg, saved_cookie_offset, 4); 605 ManagedRegister out_reg = end_jni_conv->CurrentParamRegister(); local 606 __ CreateHandleScopeEntry(out_reg, locked_object_handle_scope_offset 693 ManagedRegister out_reg = jni_conv->CurrentParamRegister(); local 717 ManagedRegister out_reg = jni_conv->CurrentParamRegister(); local [all...] |
/art/compiler/utils/x86_64/ |
jni_macro_assembler_x86_64.cc | 478 X86_64ManagedRegister out_reg = mout_reg.AsX86_64(); local 481 // Use out_reg as indicator of null. 482 in_reg = out_reg; 487 CHECK(out_reg.IsCpuRegister()); 491 if (!out_reg.Equals(in_reg)) { 492 __ xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister()); 496 __ leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset)); 499 __ leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset)); 525 X86_64ManagedRegister out_reg = mout_reg.AsX86_64() local [all...] |
jni_macro_assembler_x86_64.h | 151 // Set up out_reg to hold a Object** into the handle scope, or to be null if the 155 void CreateHandleScopeEntry(ManagedRegister out_reg,
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/art/compiler/utils/x86/ |
jni_macro_assembler_x86.cc | 427 X86ManagedRegister out_reg = mout_reg.AsX86(); local 430 CHECK(out_reg.IsCpuRegister()); 434 if (!out_reg.Equals(in_reg)) { 435 __ xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister()); 439 __ leal(out_reg.AsCpuRegister(), Address(ESP, handle_scope_offset)); 442 __ leal(out_reg.AsCpuRegister(), Address(ESP, handle_scope_offset)); 468 X86ManagedRegister out_reg = mout_reg.AsX86(); local 470 CHECK(out_reg.IsCpuRegister()); 473 if (!out_reg.Equals(in_reg)) [all...] |
jni_macro_assembler_x86.h | 129 // Set up out_reg to hold a Object** into the handle scope, or to be null if the 133 void CreateHandleScopeEntry(ManagedRegister out_reg, FrameOffset handlescope_offset,
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/external/mesa3d/src/mesa/drivers/dri/r200/ |
r200_vertprog.h | 111 #define MAKE_VSF_OP(op, out_reg, out_reg_fields) \ 112 ((op) | (out_reg) | ((out_reg_fields) << 20) )
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/art/compiler/utils/arm64/ |
jni_macro_assembler_arm64.cc | 561 Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); local 565 CHECK(out_reg.IsXRegister()) << out_reg; 569 // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset) 571 LoadWFromOffset(kLoadWord, out_reg.AsOverlappingWRegister(), SP, 573 in_reg = out_reg; 576 if (!out_reg.Equals(in_reg)) { 577 LoadImmediate(out_reg.AsXRegister(), 0, eq); 579 AddConstant(out_reg.AsXRegister(), SP, handle_scope_offs.Int32Value(), ne); 581 AddConstant(out_reg.AsXRegister(), SP, handle_scope_offs.Int32Value(), al) 608 Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); local [all...] |
jni_macro_assembler_arm64.h | 141 // Set up out_reg to hold a Object** into the handle scope, or to be null if the 145 void CreateHandleScopeEntry(ManagedRegister out_reg,
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/art/compiler/utils/arm/ |
jni_macro_assembler_arm_vixl.cc | 486 vixl::aarch32::Register out_reg = AsVIXLRegister(mout_reg.AsArm()); local 490 temps.Exclude(out_reg); 494 // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset) 496 asm_.LoadFromOffset(kLoadWord, out_reg, sp, handle_scope_offset.Int32Value()); 497 in_reg = out_reg; 504 if (!out_reg.Is(in_reg)) { 509 ___ mov(eq, out_reg, 0); 510 asm_.AddConstantInIt(out_reg, sp, handle_scope_offset.Int32Value(), ne); 516 asm_.AddConstantInIt(out_reg, sp, handle_scope_offset.Int32Value(), ne); 523 asm_.AddConstant(out_reg, sp, handle_scope_offset.Int32Value()) [all...] |
jni_macro_assembler_arm_vixl.h | 159 // Set up out_reg to hold a Object** into the handle scope, or to be null if the 163 void CreateHandleScopeEntry(ManagedRegister out_reg,
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/external/u-boot/drivers/gpio/ |
tca642x.c | 98 uint8_t out_reg = tca642x_regs[gpio_bank].output_reg; local 100 return tca642x_reg_write(chip, out_reg, reg_bit, data);
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/art/compiler/utils/ |
jni_macro_assembler.h | 176 // Set up out_reg to hold a Object** into the handle scope, or to be null if the 180 virtual void CreateHandleScopeEntry(ManagedRegister out_reg,
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/art/compiler/optimizing/ |
instruction_builder.h | 133 void BuildCheckedDivRem(uint16_t out_reg,
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code_generator_arm_vixl.cc | 4264 vixl32::Register out_reg = OutputRegister(rem); local 4572 vixl32::Register out_reg = RegisterFrom(locations->Out()); local 4841 vixl32::Register out_reg = OutputRegister(op); local 7978 vixl32::Register out_reg = RegisterFrom(out); local 8196 vixl32::Register out_reg = OutputRegister(instruction); local 8230 vixl32::Register out_reg = OutputRegister(instruction); local 8267 vixl32::Register out_reg = RegisterFrom(out); local 8281 __ Mov(RegisterFrom(maybe_temp), out_reg); local 8301 vixl32::Register out_reg = RegisterFrom(out); local [all...] |
code_generator_arm64.cc | [all...] |
intrinsics_arm64.cc | 596 Register out_reg = is_double ? XRegisterFrom(l->Out()) : WRegisterFrom(l->Out()); local 600 __ Fcvtas(out_reg, in_reg); 603 __ Tbz(out_reg, out_reg.GetSizeInBits() - 1, &done); 607 // If input is a negative tie, out_reg += 1. 611 __ Cinc(out_reg, out_reg, eq); [all...] |
intrinsics_arm_vixl.cc | 467 vixl32::Register out_reg = OutputRegister(invoke); local 475 __ Vmov(out_reg, temp1); 478 __ Cmp(out_reg, 0); 483 // If input is a negative tie, change rounding direction to positive infinity, out_reg += 1. 495 __ add(eq, out_reg, out_reg, 1); [all...] |
code_generator_mips64.cc | [all...] |
code_generator_x86.cc | 7645 Register out_reg = out.AsRegister<Register>(); local 7678 Register out_reg = out.AsRegister<Register>(); local [all...] |
code_generator_x86_64.cc | 6949 CpuRegister out_reg = out.AsRegister<CpuRegister>(); local 6982 CpuRegister out_reg = out.AsRegister<CpuRegister>(); local [all...] |
/external/v8/src/interpreter/ |
bytecode-generator.h | 238 void BuildLoadPropertyKey(LiteralProperty* property, Register out_reg);
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/art/compiler/utils/mips64/ |
assembler_mips64.cc | 3956 Mips64ManagedRegister out_reg = mout_reg.AsMips64(); local 4006 Mips64ManagedRegister out_reg = mout_reg.AsMips64(); local [all...] |
/art/oatdump/ |
oatdump.cc | [all...] |
/art/compiler/utils/mips/ |
assembler_mips.cc | 5121 MipsManagedRegister out_reg = mout_reg.AsMips(); local 5170 MipsManagedRegister out_reg = mout_reg.AsMips(); local [all...] |