1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * MCF5329 Internal Memory Map 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew (at) freescale.com) 7 */ 8 9 #ifndef __IMMAP_5329__ 10 #define __IMMAP_5329__ 11 12 #define MMAP_SCM1 0xEC000000 13 #define MMAP_MDHA 0xEC080000 14 #define MMAP_SKHA 0xEC084000 15 #define MMAP_RNG 0xEC088000 16 #define MMAP_SCM2 0xFC000000 17 #define MMAP_XBS 0xFC004000 18 #define MMAP_FBCS 0xFC008000 19 #define MMAP_CAN 0xFC020000 20 #define MMAP_FEC 0xFC030000 21 #define MMAP_SCM3 0xFC040000 22 #define MMAP_EDMA 0xFC044000 23 #define MMAP_TCD 0xFC045000 24 #define MMAP_INTC0 0xFC048000 25 #define MMAP_INTC1 0xFC04C000 26 #define MMAP_INTCACK 0xFC054000 27 #define MMAP_I2C 0xFC058000 28 #define MMAP_QSPI 0xFC05C000 29 #define MMAP_UART0 0xFC060000 30 #define MMAP_UART1 0xFC064000 31 #define MMAP_UART2 0xFC068000 32 #define MMAP_DTMR0 0xFC070000 33 #define MMAP_DTMR1 0xFC074000 34 #define MMAP_DTMR2 0xFC078000 35 #define MMAP_DTMR3 0xFC07C000 36 #define MMAP_PIT0 0xFC080000 37 #define MMAP_PIT1 0xFC084000 38 #define MMAP_PIT2 0xFC088000 39 #define MMAP_PIT3 0xFC08C000 40 #define MMAP_PWM 0xFC090000 41 #define MMAP_EPORT 0xFC094000 42 #define MMAP_WDOG 0xFC098000 43 #define MMAP_RCM 0xFC0A0000 44 #define MMAP_CCM 0xFC0A0004 45 #define MMAP_GPIO 0xFC0A4000 46 #define MMAP_RTC 0xFC0A8000 47 #define MMAP_LCDC 0xFC0AC000 48 #define MMAP_USBOTG 0xFC0B0000 49 #define MMAP_USBH 0xFC0B4000 50 #define MMAP_SDRAM 0xFC0B8000 51 #define MMAP_SSI 0xFC0BC000 52 #define MMAP_PLL 0xFC0C0000 53 54 #include <asm/coldfire/crossbar.h> 55 #include <asm/coldfire/edma.h> 56 #include <asm/coldfire/eport.h> 57 #include <asm/coldfire/qspi.h> 58 #include <asm/coldfire/flexbus.h> 59 #include <asm/coldfire/flexcan.h> 60 #include <asm/coldfire/intctrl.h> 61 #include <asm/coldfire/lcd.h> 62 #include <asm/coldfire/mdha.h> 63 #include <asm/coldfire/pwm.h> 64 #include <asm/coldfire/ssi.h> 65 #include <asm/coldfire/skha.h> 66 67 /* System control module registers */ 68 typedef struct scm1_ctrl { 69 u32 mpr0; /* 0x00 Master Privilege Register 0 */ 70 u32 res1[15]; /* 0x04 - 0x3F */ 71 u32 pacrh; /* 0x40 Peripheral Access Control Register H */ 72 u32 res2[3]; /* 0x44 - 0x53 */ 73 u32 bmt0; /*0x54 Bus Monitor Timeout 0 */ 74 } scm1_t; 75 76 /* System control module registers 2 */ 77 typedef struct scm2_ctrl { 78 u32 mpr1; /* 0x00 Master Privilege Register */ 79 u32 res1[7]; /* 0x04 - 0x1F */ 80 u32 pacra; /* 0x20 Peripheral Access Control Register A */ 81 u32 pacrb; /* 0x24 Peripheral Access Control Register B */ 82 u32 pacrc; /* 0x28 Peripheral Access Control Register C */ 83 u32 pacrd; /* 0x2C Peripheral Access Control Register D */ 84 u32 res2[4]; /* 0x30 - 0x3F */ 85 u32 pacre; /* 0x40 Peripheral Access Control Register E */ 86 u32 pacrf; /* 0x44 Peripheral Access Control Register F */ 87 u32 pacrg; /* 0x48 Peripheral Access Control Register G */ 88 u32 res3[2]; /* 0x4C - 0x53 */ 89 u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */ 90 } scm2_t; 91 92 /* System Control Module register 3 */ 93 typedef struct scm3_ctrl { 94 u8 res1[19]; /* 0x00 - 0x12 */ 95 u8 wcr; /* 0x13 wakeup control register */ 96 u16 res2; /* 0x14 - 0x15 */ 97 u16 cwcr; /* 0x16 Core Watchdog Control Register */ 98 u8 res3[3]; /* 0x18 - 0x1A */ 99 u8 cwsr; /* 0x1B Core Watchdog Service Register */ 100 u8 res4[2]; /* 0x1C - 0x1D */ 101 u8 scmisr; /* 0x1F Interrupt Status Register */ 102 u32 res5; /* 0x20 */ 103 u32 bcr; /* 0x24 Burst Configuration Register */ 104 u32 res6[18]; /* 0x28 - 0x6F */ 105 u32 cfadr; /* 0x70 Core Fault Address Register */ 106 u8 res7[4]; /* 0x71 - 0x74 */ 107 u8 cfier; /* 0x75 Core Fault Interrupt Enable Register */ 108 u8 cfloc; /* 0x76 Core Fault Location Register */ 109 u8 cfatr; /* 0x77 Core Fault Attributes Register */ 110 u32 res8; /* 0x78 */ 111 u32 cfdtr; /* 0x7C Core Fault Data Register */ 112 } scm3_t; 113 114 typedef struct canex_ctrl { 115 can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ 116 } canex_t; 117 118 /* Watchdog registers */ 119 typedef struct wdog_ctrl { 120 u16 cr; /* 0x00 Control register */ 121 u16 mr; /* 0x02 Modulus register */ 122 u16 cntr; /* 0x04 Count register */ 123 u16 sr; /* 0x06 Service register */ 124 } wdog_t; 125 126 /*Chip configuration module registers */ 127 typedef struct ccm_ctrl { 128 u16 ccr; /* 0x00 Chip configuration register */ 129 u16 res2; /* 0x02 */ 130 u16 rcon; /* 0x04 Rreset configuration register */ 131 u16 cir; /* 0x06 Chip identification register */ 132 u32 res3; /* 0x08 */ 133 u16 misccr; /* 0x0A Miscellaneous control register */ 134 u16 cdr; /* 0x0C Clock divider register */ 135 u16 uhcsr; /* 0x10 USB Host controller status register */ 136 u16 uocsr; /* 0x12 USB On-the-Go Controller Status Reg */ 137 } ccm_t; 138 139 typedef struct rcm { 140 u8 rcr; 141 u8 rsr; 142 } rcm_t; 143 144 /* GPIO port registers */ 145 typedef struct gpio_ctrl { 146 /* Port Output Data Registers */ 147 #ifdef CONFIG_M5329 148 u8 podr_fech; /* 0x00 */ 149 u8 podr_fecl; /* 0x01 */ 150 #else 151 u16 res00; /* 0x00 - 0x01 */ 152 #endif 153 u8 podr_ssi; /* 0x02 */ 154 u8 podr_busctl; /* 0x03 */ 155 u8 podr_be; /* 0x04 */ 156 u8 podr_cs; /* 0x05 */ 157 u8 podr_pwm; /* 0x06 */ 158 u8 podr_feci2c; /* 0x07 */ 159 u8 res08; /* 0x08 */ 160 u8 podr_uart; /* 0x09 */ 161 u8 podr_qspi; /* 0x0A */ 162 u8 podr_timer; /* 0x0B */ 163 #ifdef CONFIG_M5329 164 u8 res0C; /* 0x0C */ 165 u8 podr_lcddatah; /* 0x0D */ 166 u8 podr_lcddatam; /* 0x0E */ 167 u8 podr_lcddatal; /* 0x0F */ 168 u8 podr_lcdctlh; /* 0x10 */ 169 u8 podr_lcdctll; /* 0x11 */ 170 #else 171 u16 res0C; /* 0x0C - 0x0D */ 172 u8 podr_fech; /* 0x0E */ 173 u8 podr_fecl; /* 0x0F */ 174 u16 res10[3]; /* 0x10 - 0x15 */ 175 #endif 176 177 /* Port Data Direction Registers */ 178 #ifdef CONFIG_M5329 179 u16 res12; /* 0x12 - 0x13 */ 180 u8 pddr_fech; /* 0x14 */ 181 u8 pddr_fecl; /* 0x15 */ 182 #endif 183 u8 pddr_ssi; /* 0x16 */ 184 u8 pddr_busctl; /* 0x17 */ 185 u8 pddr_be; /* 0x18 */ 186 u8 pddr_cs; /* 0x19 */ 187 u8 pddr_pwm; /* 0x1A */ 188 u8 pddr_feci2c; /* 0x1B */ 189 u8 res1C; /* 0x1C */ 190 u8 pddr_uart; /* 0x1D */ 191 u8 pddr_qspi; /* 0x1E */ 192 u8 pddr_timer; /* 0x1F */ 193 #ifdef CONFIG_M5329 194 u8 res20; /* 0x20 */ 195 u8 pddr_lcddatah; /* 0x21 */ 196 u8 pddr_lcddatam; /* 0x22 */ 197 u8 pddr_lcddatal; /* 0x23 */ 198 u8 pddr_lcdctlh; /* 0x24 */ 199 u8 pddr_lcdctll; /* 0x25 */ 200 u16 res26; /* 0x26 - 0x27 */ 201 #else 202 u16 res20; /* 0x20 - 0x21 */ 203 u8 pddr_fech; /* 0x22 */ 204 u8 pddr_fecl; /* 0x23 */ 205 u16 res24[3]; /* 0x24 - 0x29 */ 206 #endif 207 208 /* Port Data Direction Registers */ 209 #ifdef CONFIG_M5329 210 u8 ppd_fech; /* 0x28 */ 211 u8 ppd_fecl; /* 0x29 */ 212 #endif 213 u8 ppd_ssi; /* 0x2A */ 214 u8 ppd_busctl; /* 0x2B */ 215 u8 ppd_be; /* 0x2C */ 216 u8 ppd_cs; /* 0x2D */ 217 u8 ppd_pwm; /* 0x2E */ 218 u8 ppd_feci2c; /* 0x2F */ 219 u8 res30; /* 0x30 */ 220 u8 ppd_uart; /* 0x31 */ 221 u8 ppd_qspi; /* 0x32 */ 222 u8 ppd_timer; /* 0x33 */ 223 #ifdef CONFIG_M5329 224 u8 res34; /* 0x34 */ 225 u8 ppd_lcddatah; /* 0x35 */ 226 u8 ppd_lcddatam; /* 0x36 */ 227 u8 ppd_lcddatal; /* 0x37 */ 228 u8 ppd_lcdctlh; /* 0x38 */ 229 u8 ppd_lcdctll; /* 0x39 */ 230 u16 res3A; /* 0x3A - 0x3B */ 231 #else 232 u16 res34; /* 0x34 - 0x35 */ 233 u8 ppd_fech; /* 0x36 */ 234 u8 ppd_fecl; /* 0x37 */ 235 u16 res38[3]; /* 0x38 - 0x3D */ 236 #endif 237 238 /* Port Clear Output Data Registers */ 239 #ifdef CONFIG_M5329 240 u8 res3C; /* 0x3C */ 241 u8 pclrr_fech; /* 0x3D */ 242 u8 pclrr_fecl; /* 0x3E */ 243 #else 244 u8 pclrr_ssi; /* 0x3E */ 245 #endif 246 u8 pclrr_busctl; /* 0x3F */ 247 u8 pclrr_be; /* 0x40 */ 248 u8 pclrr_cs; /* 0x41 */ 249 u8 pclrr_pwm; /* 0x42 */ 250 u8 pclrr_feci2c; /* 0x43 */ 251 u8 res44; /* 0x44 */ 252 u8 pclrr_uart; /* 0x45 */ 253 u8 pclrr_qspi; /* 0x46 */ 254 u8 pclrr_timer; /* 0x47 */ 255 #ifdef CONFIG_M5329 256 u8 pclrr_lcddatah; /* 0x48 */ 257 u8 pclrr_lcddatam; /* 0x49 */ 258 u8 pclrr_lcddatal; /* 0x4A */ 259 u8 pclrr_ssi; /* 0x4B */ 260 u8 pclrr_lcdctlh; /* 0x4C */ 261 u8 pclrr_lcdctll; /* 0x4D */ 262 u16 res4E; /* 0x4E - 0x4F */ 263 #else 264 u16 res48; /* 0x48 - 0x49 */ 265 u8 pclrr_fech; /* 0x4A */ 266 u8 pclrr_fecl; /* 0x4B */ 267 u8 res4C[5]; /* 0x4C - 0x50 */ 268 #endif 269 270 /* Pin Assignment Registers */ 271 #ifdef CONFIG_M5329 272 u8 par_fec; /* 0x50 */ 273 #endif 274 u8 par_pwm; /* 0x51 */ 275 u8 par_busctl; /* 0x52 */ 276 u8 par_feci2c; /* 0x53 */ 277 u8 par_be; /* 0x54 */ 278 u8 par_cs; /* 0x55 */ 279 u16 par_ssi; /* 0x56 */ 280 u16 par_uart; /* 0x58 */ 281 u16 par_qspi; /* 0x5A */ 282 u8 par_timer; /* 0x5C */ 283 #ifdef CONFIG_M5329 284 u8 par_lcddata; /* 0x5D */ 285 u16 par_lcdctl; /* 0x5E */ 286 #else 287 u8 par_fec; /* 0x5D */ 288 u16 res5E; /* 0x5E - 0x5F */ 289 #endif 290 u16 par_irq; /* 0x60 */ 291 u16 res62; /* 0x62 - 0x63 */ 292 293 /* Mode Select Control Registers */ 294 u8 mscr_flexbus; /* 0x64 */ 295 u8 mscr_sdram; /* 0x65 */ 296 u16 res66; /* 0x66 - 0x67 */ 297 298 /* Drive Strength Control Registers */ 299 u8 dscr_i2c; /* 0x68 */ 300 u8 dscr_pwm; /* 0x69 */ 301 u8 dscr_fec; /* 0x6A */ 302 u8 dscr_uart; /* 0x6B */ 303 u8 dscr_qspi; /* 0x6C */ 304 u8 dscr_timer; /* 0x6D */ 305 u8 dscr_ssi; /* 0x6E */ 306 #ifdef CONFIG_M5329 307 u8 dscr_lcd; /* 0x6F */ 308 #else 309 u8 res6F; /* 0x6F */ 310 #endif 311 u8 dscr_debug; /* 0x70 */ 312 u8 dscr_clkrst; /* 0x71 */ 313 u8 dscr_irq; /* 0x72 */ 314 } gpio_t; 315 316 /* USB OTG module registers */ 317 typedef struct usb_otg { 318 u32 id; /* 0x000 Identification Register */ 319 u32 hwgeneral; /* 0x004 General HW Parameters */ 320 u32 hwhost; /* 0x008 Host HW Parameters */ 321 u32 hwdev; /* 0x00C Device HW parameters */ 322 u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */ 323 u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */ 324 u32 res1[58]; /* 0x18 - 0xFF */ 325 u8 caplength; /* 0x100 Capability Register Length */ 326 u8 res2; /* 0x101 */ 327 u16 hciver; /* 0x102 Host Interface Version Number */ 328 u32 hcsparams; /* 0x104 Host Structural Parameters */ 329 u32 hccparams; /* 0x108 Host Capability Parameters */ 330 u32 res3[5]; /* 0x10C - 0x11F */ 331 u16 dciver; /* 0x120 Device Interface Version Number */ 332 u16 res4; /* 0x122 */ 333 u32 dccparams; /* 0x124 Device Capability Parameters */ 334 u32 res5[6]; /* 0x128 - 0x13F */ 335 u32 cmd; /* 0x140 USB Command */ 336 u32 sts; /* 0x144 USB Status */ 337 u32 intr; /* 0x148 USB Interrupt Enable */ 338 u32 frindex; /* 0x14C USB Frame Index */ 339 u32 res6; /* 0x150 */ 340 u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */ 341 u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */ 342 u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */ 343 u32 burstsize; /* 0x160 Master Interface Data Burst Size */ 344 u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */ 345 u32 res7[6]; /* 0x168 - 0x17F */ 346 u32 cfgflag; /* 0x180 Configure Flag Register */ 347 u32 portsc1; /* 0x184 Port Status/Control */ 348 u32 res8[7]; /* 0x188 - 0x1A3 */ 349 u32 otgsc; /* 0x1A4 On The Go Status and Control */ 350 u32 mode; /* 0x1A8 USB mode register */ 351 u32 eptsetstat; /* 0x1AC Endpoint Setup status */ 352 u32 eptprime; /* 0x1B0 Endpoint initialization */ 353 u32 eptflush; /* 0x1B4 Endpoint de-initialize */ 354 u32 eptstat; /* 0x1B8 Endpoint status */ 355 u32 eptcomplete; /* 0x1BC Endpoint Complete */ 356 u32 eptctrl0; /* 0x1C0 Endpoint control 0 */ 357 u32 eptctrl1; /* 0x1C4 Endpoint control 1 */ 358 u32 eptctrl2; /* 0x1C8 Endpoint control 2 */ 359 u32 eptctrl3; /* 0x1CC Endpoint control 3 */ 360 } usbotg_t; 361 362 /* SDRAM controller registers */ 363 typedef struct sdram_ctrl { 364 u32 mode; /* 0x00 Mode/Extended Mode register */ 365 u32 ctrl; /* 0x04 Control register */ 366 u32 cfg1; /* 0x08 Configuration register 1 */ 367 u32 cfg2; /* 0x0C Configuration register 2 */ 368 u32 res1[64]; /* 0x10 - 0x10F */ 369 u32 cs0; /* 0x110 Chip Select 0 Configuration */ 370 u32 cs1; /* 0x114 Chip Select 1 Configuration */ 371 } sdram_t; 372 373 /* Clock Module registers */ 374 typedef struct pll_ctrl { 375 u8 podr; /* 0x00 Output Divider Register */ 376 u8 res1[3]; 377 u8 pcr; /* 0x04 Control Register */ 378 u8 res2[3]; 379 u8 pmdr; /* 0x08 Modulation Divider Register */ 380 u8 res3[3]; 381 u8 pfdr; /* 0x0C Feedback Divider Register */ 382 u8 res4[3]; 383 } pll_t; 384 385 #endif /* __IMMAP_5329__ */ 386
