1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __SPM_H__ 7 #define __SPM_H__ 8 9 #define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000) 10 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010) 11 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014) 12 #define SPM_CLK_SETTLE (SPM_BASE + 0x100) 13 #define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218) 14 #define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c) 15 #define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220) 16 #define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264) 17 #define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c) 18 #define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274) 19 #define SPM_MD32_SRAM_CON (SPM_BASE + 0x2c8) 20 #define SPM_PCM_CON0 (SPM_BASE + 0x310) 21 #define SPM_PCM_CON1 (SPM_BASE + 0x314) 22 #define SPM_PCM_IM_PTR (SPM_BASE + 0x318) 23 #define SPM_PCM_IM_LEN (SPM_BASE + 0x31c) 24 #define SPM_PCM_REG_DATA_INI (SPM_BASE + 0x320) 25 #define SPM_PCM_EVENT_VECTOR0 (SPM_BASE + 0x340) 26 #define SPM_PCM_EVENT_VECTOR1 (SPM_BASE + 0x344) 27 #define SPM_PCM_EVENT_VECTOR2 (SPM_BASE + 0x348) 28 #define SPM_PCM_EVENT_VECTOR3 (SPM_BASE + 0x34c) 29 #define SPM_PCM_MAS_PAUSE_MASK (SPM_BASE + 0x354) 30 #define SPM_PCM_PWR_IO_EN (SPM_BASE + 0x358) 31 #define SPM_PCM_TIMER_VAL (SPM_BASE + 0x35c) 32 #define SPM_PCM_TIMER_OUT (SPM_BASE + 0x360) 33 #define SPM_PCM_REG0_DATA (SPM_BASE + 0x380) 34 #define SPM_PCM_REG1_DATA (SPM_BASE + 0x384) 35 #define SPM_PCM_REG2_DATA (SPM_BASE + 0x388) 36 #define SPM_PCM_REG3_DATA (SPM_BASE + 0x38c) 37 #define SPM_PCM_REG4_DATA (SPM_BASE + 0x390) 38 #define SPM_PCM_REG5_DATA (SPM_BASE + 0x394) 39 #define SPM_PCM_REG6_DATA (SPM_BASE + 0x398) 40 #define SPM_PCM_REG7_DATA (SPM_BASE + 0x39c) 41 #define SPM_PCM_REG8_DATA (SPM_BASE + 0x3a0) 42 #define SPM_PCM_REG9_DATA (SPM_BASE + 0x3a4) 43 #define SPM_PCM_REG10_DATA (SPM_BASE + 0x3a8) 44 #define SPM_PCM_REG11_DATA (SPM_BASE + 0x3ac) 45 #define SPM_PCM_REG12_DATA (SPM_BASE + 0x3b0) 46 #define SPM_PCM_REG13_DATA (SPM_BASE + 0x3b4) 47 #define SPM_PCM_REG14_DATA (SPM_BASE + 0x3b8) 48 #define SPM_PCM_REG15_DATA (SPM_BASE + 0x3bc) 49 #define SPM_PCM_EVENT_REG_STA (SPM_BASE + 0x3c0) 50 #define SPM_PCM_FSM_STA (SPM_BASE + 0x3c4) 51 #define SPM_PCM_IM_HOST_RW_PTR (SPM_BASE + 0x3c8) 52 #define SPM_PCM_IM_HOST_RW_DAT (SPM_BASE + 0x3cc) 53 #define SPM_PCM_EVENT_VECTOR4 (SPM_BASE + 0x3d0) 54 #define SPM_PCM_EVENT_VECTOR5 (SPM_BASE + 0x3d4) 55 #define SPM_PCM_EVENT_VECTOR6 (SPM_BASE + 0x3d8) 56 #define SPM_PCM_EVENT_VECTOR7 (SPM_BASE + 0x3dc) 57 #define SPM_PCM_SW_INT_SET (SPM_BASE + 0x3e0) 58 #define SPM_PCM_SW_INT_CLEAR (SPM_BASE + 0x3e4) 59 #define SPM_CLK_CON (SPM_BASE + 0x400) 60 #define SPM_SLEEP_PTPOD2_CON (SPM_BASE + 0x408) 61 #define SPM_APMCU_PWRCTL (SPM_BASE + 0x600) 62 #define SPM_AP_DVFS_CON_SET (SPM_BASE + 0x604) 63 #define SPM_AP_STANBY_CON (SPM_BASE + 0x608) 64 #define SPM_PWR_STATUS (SPM_BASE + 0x60c) 65 #define SPM_PWR_STATUS_2ND (SPM_BASE + 0x610) 66 #define SPM_AP_BSI_REQ (SPM_BASE + 0x614) 67 #define SPM_SLEEP_TIMER_STA (SPM_BASE + 0x720) 68 #define SPM_SLEEP_WAKEUP_EVENT_MASK (SPM_BASE + 0x810) 69 #define SPM_SLEEP_CPU_WAKEUP_EVENT (SPM_BASE + 0x814) 70 #define SPM_SLEEP_MD32_WAKEUP_EVENT_MASK (SPM_BASE + 0x818) 71 #define SPM_PCM_WDT_TIMER_VAL (SPM_BASE + 0x824) 72 #define SPM_PCM_WDT_TIMER_OUT (SPM_BASE + 0x828) 73 #define SPM_PCM_MD32_MAILBOX (SPM_BASE + 0x830) 74 #define SPM_PCM_MD32_IRQ (SPM_BASE + 0x834) 75 #define SPM_SLEEP_ISR_MASK (SPM_BASE + 0x900) 76 #define SPM_SLEEP_ISR_STATUS (SPM_BASE + 0x904) 77 #define SPM_SLEEP_ISR_RAW_STA (SPM_BASE + 0x910) 78 #define SPM_SLEEP_MD32_ISR_RAW_STA (SPM_BASE + 0x914) 79 #define SPM_SLEEP_WAKEUP_MISC (SPM_BASE + 0x918) 80 #define SPM_SLEEP_BUS_PROTECT_RDY (SPM_BASE + 0x91c) 81 #define SPM_SLEEP_SUBSYS_IDLE_STA (SPM_BASE + 0x920) 82 #define SPM_PCM_RESERVE (SPM_BASE + 0xb00) 83 #define SPM_PCM_RESERVE2 (SPM_BASE + 0xb04) 84 #define SPM_PCM_FLAGS (SPM_BASE + 0xb08) 85 #define SPM_PCM_SRC_REQ (SPM_BASE + 0xb0c) 86 #define SPM_PCM_DEBUG_CON (SPM_BASE + 0xb20) 87 #define SPM_CA7_CPU0_IRQ_MASK (SPM_BASE + 0xb30) 88 #define SPM_CA7_CPU1_IRQ_MASK (SPM_BASE + 0xb34) 89 #define SPM_CA7_CPU2_IRQ_MASK (SPM_BASE + 0xb38) 90 #define SPM_CA7_CPU3_IRQ_MASK (SPM_BASE + 0xb3c) 91 #define SPM_CA15_CPU0_IRQ_MASK (SPM_BASE + 0xb40) 92 #define SPM_CA15_CPU1_IRQ_MASK (SPM_BASE + 0xb44) 93 #define SPM_CA15_CPU2_IRQ_MASK (SPM_BASE + 0xb48) 94 #define SPM_CA15_CPU3_IRQ_MASK (SPM_BASE + 0xb4c) 95 #define SPM_PCM_PASR_DPD_0 (SPM_BASE + 0xb60) 96 #define SPM_PCM_PASR_DPD_1 (SPM_BASE + 0xb64) 97 #define SPM_PCM_PASR_DPD_2 (SPM_BASE + 0xb68) 98 #define SPM_PCM_PASR_DPD_3 (SPM_BASE + 0xb6c) 99 #define SPM_SLEEP_CA7_WFI0_EN (SPM_BASE + 0xf00) 100 #define SPM_SLEEP_CA7_WFI1_EN (SPM_BASE + 0xf04) 101 #define SPM_SLEEP_CA7_WFI2_EN (SPM_BASE + 0xf08) 102 #define SPM_SLEEP_CA7_WFI3_EN (SPM_BASE + 0xf0c) 103 #define SPM_SLEEP_CA15_WFI0_EN (SPM_BASE + 0xf10) 104 #define SPM_SLEEP_CA15_WFI1_EN (SPM_BASE + 0xf14) 105 #define SPM_SLEEP_CA15_WFI2_EN (SPM_BASE + 0xf18) 106 #define SPM_SLEEP_CA15_WFI3_EN (SPM_BASE + 0xf1c) 107 108 #define AP_PLL_CON3 0x1020900c 109 #define AP_PLL_CON4 0x10209010 110 111 #define SPM_PROJECT_CODE 0xb16 112 113 #define SPM_REGWR_EN (1U << 0) 114 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) 115 116 #define SPM_CPU_PDN_DIS (1U << 0) 117 #define SPM_INFRA_PDN_DIS (1U << 1) 118 #define SPM_DDRPHY_PDN_DIS (1U << 2) 119 #define SPM_DUALVCORE_PDN_DIS (1U << 3) 120 #define SPM_PASR_DIS (1U << 4) 121 #define SPM_DPD_DIS (1U << 5) 122 #define SPM_SODI_DIS (1U << 6) 123 #define SPM_MEMPLL_RESET (1U << 7) 124 #define SPM_MAINPLL_PDN_DIS (1U << 8) 125 #define SPM_CPU_DVS_DIS (1U << 9) 126 #define SPM_CPU_DORMANT (1U << 10) 127 #define SPM_EXT_VSEL_GPIO103 (1U << 11) 128 #define SPM_DDR_HIGH_SPEED (1U << 12) 129 #define SPM_OPT (1U << 13) 130 131 #define POWER_ON_VAL1_DEF 0x01011820 132 #define PCM_FSM_STA_DEF 0x48490 133 #define PCM_END_FSM_STA_DEF 0x08490 134 #define PCM_END_FSM_STA_MASK 0x3fff0 135 #define PCM_HANDSHAKE_SEND1 0xbeefbeef 136 137 #define PCM_WDT_TIMEOUT (30 * 32768) 138 #define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) 139 140 #define CON0_PCM_KICK (1U << 0) 141 #define CON0_IM_KICK (1U << 1) 142 #define CON0_IM_SLEEP_DVS (1U << 3) 143 #define CON0_PCM_SW_RESET (1U << 15) 144 #define CON0_CFG_KEY (SPM_PROJECT_CODE << 16) 145 146 #define CON1_IM_SLAVE (1U << 0) 147 #define CON1_MIF_APBEN (1U << 3) 148 #define CON1_PCM_TIMER_EN (1U << 5) 149 #define CON1_IM_NONRP_EN (1U << 6) 150 #define CON1_PCM_WDT_EN (1U << 8) 151 #define CON1_PCM_WDT_WAKE_MODE (1U << 9) 152 #define CON1_SPM_SRAM_SLP_B (1U << 10) 153 #define CON1_SPM_SRAM_ISO_B (1U << 11) 154 #define CON1_EVENT_LOCK_EN (1U << 12) 155 #define CON1_CFG_KEY (SPM_PROJECT_CODE << 16) 156 157 #define PCM_PWRIO_EN_R0 (1U << 0) 158 #define PCM_PWRIO_EN_R7 (1U << 7) 159 #define PCM_RF_SYNC_R0 (1U << 16) 160 #define PCM_RF_SYNC_R2 (1U << 18) 161 #define PCM_RF_SYNC_R6 (1U << 22) 162 #define PCM_RF_SYNC_R7 (1U << 23) 163 164 #define CC_SYSCLK0_EN_0 (1U << 0) 165 #define CC_SYSCLK0_EN_1 (1U << 1) 166 #define CC_SYSCLK1_EN_0 (1U << 2) 167 #define CC_SYSCLK1_EN_1 (1U << 3) 168 #define CC_SYSSETTLE_SEL (1U << 4) 169 #define CC_LOCK_INFRA_DCM (1U << 5) 170 #define CC_SRCLKENA_MASK_0 (1U << 6) 171 #define CC_CXO32K_RM_EN_MD1 (1U << 9) 172 #define CC_CXO32K_RM_EN_MD2 (1U << 10) 173 #define CC_CLKSQ1_SEL (1U << 12) 174 #define CC_DISABLE_DORM_PWR (1U << 14) 175 #define CC_MD32_DCM_EN (1U << 18) 176 177 #define WFI_OP_AND 1 178 #define WFI_OP_OR 0 179 180 #define WAKE_MISC_PCM_TIMER (1U << 19) 181 #define WAKE_MISC_CPU_WAKE (1U << 20) 182 183 /* define WAKE_SRC_XXX */ 184 #define WAKE_SRC_SPM_MERGE (1 << 0) 185 #define WAKE_SRC_KP (1 << 2) 186 #define WAKE_SRC_WDT (1 << 3) 187 #define WAKE_SRC_GPT (1 << 4) 188 #define WAKE_SRC_EINT (1 << 6) 189 #define WAKE_SRC_LOW_BAT (1 << 9) 190 #define WAKE_SRC_MD32 (1 << 10) 191 #define WAKE_SRC_USB_CD (1 << 14) 192 #define WAKE_SRC_USB_PDN (1 << 15) 193 #define WAKE_SRC_AFE (1 << 20) 194 #define WAKE_SRC_THERM (1 << 21) 195 #define WAKE_SRC_CIRQ (1 << 22) 196 #define WAKE_SRC_SYSPWREQ (1 << 24) 197 #define WAKE_SRC_SEJ (1 << 27) 198 #define WAKE_SRC_ALL_MD32 (1 << 28) 199 #define WAKE_SRC_CPU_IRQ (1 << 29) 200 201 enum wake_reason_t { 202 WR_NONE = 0, 203 WR_UART_BUSY = 1, 204 WR_PCM_ASSERT = 2, 205 WR_PCM_TIMER = 3, 206 WR_PCM_ABORT = 4, 207 WR_WAKE_SRC = 5, 208 WR_UNKNOWN = 6, 209 }; 210 211 struct pwr_ctrl { 212 unsigned int pcm_flags; 213 unsigned int pcm_flags_cust; 214 unsigned int pcm_reserve; 215 unsigned int timer_val; 216 unsigned int timer_val_cust; 217 unsigned int wake_src; 218 unsigned int wake_src_cust; 219 unsigned int wake_src_md32; 220 unsigned short r0_ctrl_en; 221 unsigned short r7_ctrl_en; 222 unsigned short infra_dcm_lock; 223 unsigned short pcm_apsrc_req; 224 unsigned short mcusys_idle_mask; 225 unsigned short ca15top_idle_mask; 226 unsigned short ca7top_idle_mask; 227 unsigned short wfi_op; 228 unsigned short ca15_wfi0_en; 229 unsigned short ca15_wfi1_en; 230 unsigned short ca15_wfi2_en; 231 unsigned short ca15_wfi3_en; 232 unsigned short ca7_wfi0_en; 233 unsigned short ca7_wfi1_en; 234 unsigned short ca7_wfi2_en; 235 unsigned short ca7_wfi3_en; 236 unsigned short disp_req_mask; 237 unsigned short mfg_req_mask; 238 unsigned short md32_req_mask; 239 unsigned short syspwreq_mask; 240 unsigned short srclkenai_mask; 241 }; 242 243 struct wake_status { 244 unsigned int assert_pc; 245 unsigned int r12; 246 unsigned int raw_sta; 247 unsigned int wake_misc; 248 unsigned int timer_out; 249 unsigned int r13; 250 unsigned int idle_sta; 251 unsigned int debug_flag; 252 unsigned int event_reg; 253 unsigned int isr; 254 }; 255 256 struct pcm_desc { 257 const char *version; /* PCM code version */ 258 const unsigned int *base; /* binary array base */ 259 const unsigned int size; /* binary array size */ 260 const unsigned char sess; /* session number */ 261 const unsigned char replace; /* replace mode */ 262 263 unsigned int vec0; /* event vector 0 config */ 264 unsigned int vec1; /* event vector 1 config */ 265 unsigned int vec2; /* event vector 2 config */ 266 unsigned int vec3; /* event vector 3 config */ 267 unsigned int vec4; /* event vector 4 config */ 268 unsigned int vec5; /* event vector 5 config */ 269 unsigned int vec6; /* event vector 6 config */ 270 unsigned int vec7; /* event vector 7 config */ 271 }; 272 273 struct spm_lp_scen { 274 const struct pcm_desc *pcmdesc; 275 struct pwr_ctrl *pwrctrl; 276 }; 277 278 #define EVENT_VEC(event, resume, imme, pc) \ 279 (((pc) << 16) | \ 280 (!!(imme) << 6) | \ 281 (!!(resume) << 5) | \ 282 ((event) & 0x1f)) 283 284 #define spm_read(addr) mmio_read_32(addr) 285 #define spm_write(addr, val) mmio_write_32(addr, val) 286 287 #define is_cpu_pdn(flags) (!((flags) & SPM_CPU_PDN_DIS)) 288 #define is_infra_pdn(flags) (!((flags) & SPM_INFRA_PDN_DIS)) 289 #define is_ddrphy_pdn(flags) (!((flags) & SPM_DDRPHY_PDN_DIS)) 290 291 static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl, 292 unsigned int flags) 293 { 294 flags &= ~SPM_EXT_VSEL_GPIO103; 295 296 if (pwrctrl->pcm_flags_cust == 0) 297 pwrctrl->pcm_flags = flags; 298 else 299 pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust; 300 } 301 302 static inline void set_pwrctrl_pcm_data(struct pwr_ctrl *pwrctrl, 303 unsigned int data) 304 { 305 pwrctrl->pcm_reserve = data; 306 } 307 308 void spm_reset_and_init_pcm(void); 309 310 void spm_init_pcm_register(void); /* init r0 and r7 */ 311 void spm_set_power_control(const struct pwr_ctrl *pwrctrl); 312 void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); 313 314 void spm_get_wakeup_status(struct wake_status *wakesta); 315 void spm_set_sysclk_settle(void); 316 void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl); 317 void spm_clean_after_wakeup(void); 318 enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta); 319 void spm_register_init(void); 320 void spm_go_to_hotplug(void); 321 void spm_init_event_vector(const struct pcm_desc *pcmdesc); 322 void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc); 323 void spm_set_sysclk_settle(void); 324 int is_mcdi_ready(void); 325 int is_hotplug_ready(void); 326 int is_suspend_ready(void); 327 void set_mcdi_ready(void); 328 void set_hotplug_ready(void); 329 void set_suspend_ready(void); 330 void clear_all_ready(void); 331 void spm_lock_init(void); 332 void spm_lock_get(void); 333 void spm_lock_release(void); 334 void spm_boot_init(void); 335 336 #endif /* __SPM_H__ */ 337
