| /external/u-boot/board/ti/ks2_evm/ |
| ddr3_cfg.c | 32 .pgcr2 = 0x00F07A12ul,
|
| ddr3_k2g.c | 34 .pgcr2 = 0x00F03D09ul,
74 .pgcr2 = 0x00F05159ul,
135 .pgcr2 = 0x00F03D09ul,
|
| /external/u-boot/arch/arm/mach-keystone/include/mach/ |
| ddr3.h | 32 unsigned int pgcr2; member in struct:ddr3_phy_config
|
| /external/u-boot/arch/arm/mach-sunxi/ |
| dram_sun8i_a33.c | 237 clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
286 setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
|
| dram_sun8i_a83t.c | 320 clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
378 setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
|
| /external/u-boot/arch/arm/include/asm/arch-sunxi/ |
| dram_sun8i_a23.h | 198 u32 pgcr2; /* 0x8c */ member in struct:sunxi_mctl_phy_reg
|
| dram_sun8i_a33.h | 120 u32 pgcr2; /* 0x108 */ member in struct:sunxi_mctl_ctl_reg
|
| dram_sun8i_a83t.h | 120 u32 pgcr2; /* 0x108 */ member in struct:sunxi_mctl_ctl_reg
|
| /external/u-boot/arch/arm/mach-keystone/ |
| ddr3_spd.c | 38 debug_ddr_cfg("pgcr2 0x%08X\n", ptr->pgcr2);
359 spd_cb->phy_cfg.pgcr2 = (0xF << 20) | ((int)spd->t_refprd & 0x3ffff);
|
| ddr3.c | 56 __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
|
