1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Keystone2: DDR3 initialization 4 * 5 * (C) Copyright 2012-2014 6 * Texas Instruments Incorporated, <www.ti.com> 7 */ 8 9 #include <asm/io.h> 10 #include <common.h> 11 #include <asm/arch/msmc.h> 12 #include <asm/arch/ddr3.h> 13 #include <asm/arch/psc_defs.h> 14 15 #include <asm/ti-common/ti-edma3.h> 16 17 #define DDR3_EDMA_BLK_SIZE_SHIFT 10 18 #define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT) 19 #define DDR3_EDMA_BCNT 0x8000 20 #define DDR3_EDMA_CCNT 1 21 #define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT) 22 #define DDR3_EDMA_SLOT_NUM 1 23 24 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) 25 { 26 unsigned int tmp; 27 28 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) 29 & 0x00000001) != 0x00000001) 30 ; 31 32 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); 33 34 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); 35 tmp &= ~(phy_cfg->pgcr1_mask); 36 tmp |= phy_cfg->pgcr1_val; 37 __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET); 38 39 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); 40 __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); 41 __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); 42 __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); 43 44 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); 45 tmp &= ~(phy_cfg->dcr_mask); 46 tmp |= phy_cfg->dcr_val; 47 __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET); 48 49 __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET); 50 __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET); 51 __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); 52 __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); 53 __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET); 54 __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); 55 __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET); 56 __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET); 57 58 __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET); 59 __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET); 60 __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET); 61 62 __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET); 63 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) 64 ; 65 66 if (cpu_is_k2g()) { 67 clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET, 68 phy_cfg->datx8_2_mask, 69 phy_cfg->datx8_2_val); 70 71 clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET, 72 phy_cfg->datx8_3_mask, 73 phy_cfg->datx8_3_val); 74 75 clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 76 phy_cfg->datx8_4_mask, 77 phy_cfg->datx8_4_val); 78 79 clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 80 phy_cfg->datx8_5_mask, 81 phy_cfg->datx8_5_val); 82 83 clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 84 phy_cfg->datx8_6_mask, 85 phy_cfg->datx8_6_val); 86 87 clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 88 phy_cfg->datx8_7_mask, 89 phy_cfg->datx8_7_val); 90 91 clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 92 phy_cfg->datx8_8_mask, 93 phy_cfg->datx8_8_val); 94 } 95 96 __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET); 97 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) 98 ; 99 } 100 101 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) 102 { 103 __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET); 104 __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET); 105 __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET); 106 __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET); 107 __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET); 108 __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); 109 __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); 110 } 111 112 int ddr3_ecc_support_rmw(u32 base) 113 { 114 u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET); 115 116 /* Check the DDR3 controller ID reg if the controllers 117 supports ECC RMW or not */ 118 if (value == 0x40461C02) 119 return 1; 120 121 return 0; 122 } 123 124 static void ddr3_ecc_config(u32 base, u32 value) 125 { 126 u32 data; 127 128 __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET); 129 udelay(100000); /* delay required to synchronize across clock domains */ 130 131 if (value & KS2_DDR3_ECC_EN) { 132 /* Clear the 1-bit error count */ 133 data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); 134 __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); 135 136 /* enable the ECC interrupt */ 137 __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS | 138 KS2_DDR3_WR_ECC_ERR_SYS, 139 base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET); 140 141 /* Clear the ECC error interrupt status */ 142 __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS | 143 KS2_DDR3_WR_ECC_ERR_SYS, 144 base + KS2_DDR3_ECC_INT_STATUS_OFFSET); 145 } 146 } 147 148 static void ddr3_reset_data(u32 base, u32 ddr3_size) 149 { 150 u32 mpax[2]; 151 u32 seg_num; 152 u32 seg, blks, dst, edma_blks; 153 struct edma3_slot_config slot; 154 struct edma3_channel_config edma_channel; 155 u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, }; 156 157 /* Setup an edma to copy the 1k block to the entire DDR */ 158 puts("\nClear entire DDR3 memory to enable ECC\n"); 159 160 /* save the SES MPAX regs */ 161 if (cpu_is_k2g()) 162 msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax); 163 else 164 msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax); 165 166 /* setup edma slot 1 configuration */ 167 slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB | 168 EDMA3_SLOPT_COMP_CODE(0) | 169 EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC; 170 slot.bcnt = DDR3_EDMA_BCNT; 171 slot.acnt = DDR3_EDMA_BLK_SIZE; 172 slot.ccnt = DDR3_EDMA_CCNT; 173 slot.src_bidx = 0; 174 slot.dst_bidx = DDR3_EDMA_BLK_SIZE; 175 slot.src_cidx = 0; 176 slot.dst_cidx = 0; 177 slot.link = EDMA3_PARSET_NULL_LINK; 178 slot.bcntrld = 0; 179 edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot); 180 181 /* configure quik edma channel */ 182 edma_channel.slot = DDR3_EDMA_SLOT_NUM; 183 edma_channel.chnum = 0; 184 edma_channel.complete_code = 0; 185 /* event trigger after dst update */ 186 edma_channel.trigger_slot_word = EDMA3_TWORD(dst); 187 qedma3_start(KS2_EDMA0_BASE, &edma_channel); 188 189 /* DDR3 size in segments (4KB seg size) */ 190 seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT); 191 192 for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) { 193 /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF 194 access slave interface so that edma driver can access */ 195 if (cpu_is_k2g()) { 196 msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0, 197 base >> KS2_MSMC_SEG_SIZE_SHIFT, 198 KS2_MSMC_DST_SEG_BASE + seg, 199 MPAX_SEG_2G); 200 } else { 201 msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0, 202 base >> KS2_MSMC_SEG_SIZE_SHIFT, 203 KS2_MSMC_DST_SEG_BASE + seg, 204 MPAX_SEG_2G); 205 } 206 207 if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM) 208 edma_blks = KS2_MSMC_MAP_SEG_NUM << 209 (KS2_MSMC_SEG_SIZE_SHIFT 210 - DDR3_EDMA_BLK_SIZE_SHIFT); 211 else 212 edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT 213 - DDR3_EDMA_BLK_SIZE_SHIFT); 214 215 /* Use edma driver to scrub 2GB DDR memory */ 216 for (dst = base, blks = 0; blks < edma_blks; 217 blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) { 218 edma3_set_src_addr(KS2_EDMA0_BASE, 219 edma_channel.slot, (u32)edma_src); 220 edma3_set_dest_addr(KS2_EDMA0_BASE, 221 edma_channel.slot, (u32)dst); 222 223 while (edma3_check_for_transfer(KS2_EDMA0_BASE, 224 &edma_channel)) 225 udelay(10); 226 } 227 } 228 229 qedma3_stop(KS2_EDMA0_BASE, &edma_channel); 230 231 /* restore the SES MPAX regs */ 232 if (cpu_is_k2g()) 233 msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax); 234 else 235 msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax); 236 } 237 238 static void ddr3_ecc_init_range(u32 base) 239 { 240 u32 ecc_val = KS2_DDR3_ECC_EN; 241 u32 rmw = ddr3_ecc_support_rmw(base); 242 243 if (rmw) 244 ecc_val |= KS2_DDR3_ECC_RMW_EN; 245 246 __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET); 247 248 ddr3_ecc_config(base, ecc_val); 249 } 250 251 void ddr3_enable_ecc(u32 base, int test) 252 { 253 u32 ecc_val = KS2_DDR3_ECC_ENABLE; 254 u32 rmw = ddr3_ecc_support_rmw(base); 255 256 if (test) 257 ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN; 258 259 if (!rmw) { 260 if (!test) 261 /* by default, disable ecc when rmw = 0 and no 262 ecc test */ 263 ecc_val = 0; 264 } else { 265 ecc_val |= KS2_DDR3_ECC_RMW_EN; 266 } 267 268 ddr3_ecc_config(base, ecc_val); 269 } 270 271 void ddr3_disable_ecc(u32 base) 272 { 273 ddr3_ecc_config(base, 0); 274 } 275 276 #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) 277 static void cic_init(u32 base) 278 { 279 /* Disable CIC global interrupts */ 280 __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE); 281 282 /* Set to normal mode, no nesting, no priority hold */ 283 __raw_writel(0, base + KS2_CIC_CTRL); 284 __raw_writel(0, base + KS2_CIC_HOST_CTRL); 285 286 /* Enable CIC global interrupts */ 287 __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE); 288 } 289 290 static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num) 291 { 292 /* Map the system interrupt to a CIC channel */ 293 __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num); 294 295 /* Enable CIC system interrupt */ 296 __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET); 297 298 /* Enable CIC Host interrupt */ 299 __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET); 300 } 301 302 static void ddr3_map_ecc_cic2_irq(u32 base) 303 { 304 cic_init(base); 305 cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM, 306 KS2_CIC2_DDR3_ECC_IRQ_NUM); 307 } 308 #endif 309 310 void ddr3_init_ecc(u32 base, u32 ddr3_size) 311 { 312 if (!ddr3_ecc_support_rmw(base)) { 313 ddr3_disable_ecc(base); 314 return; 315 } 316 317 ddr3_ecc_init_range(base); 318 ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size); 319 320 /* mapping DDR3 ECC system interrupt from CIC2 to GIC */ 321 #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) 322 ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE); 323 #endif 324 ddr3_enable_ecc(base, 0); 325 } 326 327 void ddr3_check_ecc_int(u32 base) 328 { 329 char *env; 330 int ecc_test = 0; 331 u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); 332 333 env = env_get("ecc_test"); 334 if (env) 335 ecc_test = simple_strtol(env, NULL, 0); 336 337 if (value & KS2_DDR3_WR_ECC_ERR_SYS) 338 puts("DDR3 ECC write error interrupted\n"); 339 340 if (value & KS2_DDR3_2B_ECC_ERR_SYS) { 341 puts("DDR3 ECC 2-bit error interrupted\n"); 342 343 if (!ecc_test) { 344 puts("Reseting the device ...\n"); 345 reset_cpu(0); 346 } 347 } 348 349 value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); 350 if (value) { 351 printf("1-bit ECC err count: 0x%x\n", value); 352 value = __raw_readl(base + 353 KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET); 354 printf("1-bit ECC err address log: 0x%x\n", value); 355 } 356 } 357 358 void ddr3_reset_ddrphy(void) 359 { 360 u32 tmp; 361 362 /* Assert DDR3A PHY reset */ 363 tmp = readl(KS2_DDR3APLLCTL1); 364 tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; 365 writel(tmp, KS2_DDR3APLLCTL1); 366 367 /* wait 10us to catch the reset */ 368 udelay(10); 369 370 /* Release DDR3A PHY reset */ 371 tmp = readl(KS2_DDR3APLLCTL1); 372 tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; 373 __raw_writel(tmp, KS2_DDR3APLLCTL1); 374 } 375 376 #ifdef CONFIG_SOC_K2HK 377 /** 378 * ddr3_reset_workaround - reset workaround in case if leveling error 379 * detected for PG 1.0 and 1.1 k2hk SoCs 380 */ 381 void ddr3_err_reset_workaround(void) 382 { 383 unsigned int tmp; 384 unsigned int tmp_a; 385 unsigned int tmp_b; 386 387 /* 388 * Check for PGSR0 error bits of DDR3 PHY. 389 * Check for WLERR, QSGERR, WLAERR, 390 * RDERR, WDERR, REERR, WEERR error to see if they are set or not 391 */ 392 tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); 393 tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); 394 395 if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) { 396 printf("DDR Leveling Error Detected!\n"); 397 printf("DDR3A PGSR0 = 0x%x\n", tmp_a); 398 printf("DDR3B PGSR0 = 0x%x\n", tmp_b); 399 400 /* 401 * Write Keys to KICK registers to enable writes to registers 402 * in boot config space 403 */ 404 __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0); 405 __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); 406 407 /* 408 * Move DDR3A Module out of reset isolation by setting 409 * MDCTL23[12] = 0 410 */ 411 tmp_a = __raw_readl(KS2_PSC_BASE + 412 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); 413 414 tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0); 415 __raw_writel(tmp_a, KS2_PSC_BASE + 416 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); 417 418 /* 419 * Move DDR3B Module out of reset isolation by setting 420 * MDCTL24[12] = 0 421 */ 422 tmp_b = __raw_readl(KS2_PSC_BASE + 423 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); 424 tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0); 425 __raw_writel(tmp_b, KS2_PSC_BASE + 426 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); 427 428 /* 429 * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes 430 * to RSTCTRL and RSTCFG 431 */ 432 tmp = __raw_readl(KS2_RSTCTRL); 433 tmp &= KS2_RSTCTRL_MASK; 434 tmp |= KS2_RSTCTRL_KEY; 435 __raw_writel(tmp, KS2_RSTCTRL); 436 437 /* 438 * Set PLL Controller to drive hard reset on SW trigger by 439 * setting RSTCFG[13] = 0 440 */ 441 tmp = __raw_readl(KS2_RSTCTRL_RSCFG); 442 tmp &= ~KS2_RSTYPE_PLL_SOFT; 443 __raw_writel(tmp, KS2_RSTCTRL_RSCFG); 444 445 reset_cpu(0); 446 } 447 } 448 #endif 449
