| /external/u-boot/arch/arm/mach-sunxi/ |
| prcm.c | 20 #include <asm/arch/prcm.h>
26 struct sunxi_prcm_reg *prcm = local
30 setbits_le32(&prcm->apb0_gate, flags);
33 setbits_le32(&prcm->apb0_reset, flags);
38 struct sunxi_prcm_reg *prcm = local
42 clrbits_le32(&prcm->apb0_reset, flags);
45 clrbits_le32(&prcm->apb0_gate, flags);
|
| clock_sun6i.c | 15 #include <asm/arch/prcm.h>
25 struct sunxi_prcm_reg * const prcm = local
29 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
31 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
34 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
68 struct sunxi_prcm_reg * const prcm = local
75 setbits_le32(&prcm->prcm_sec_switch,
|
| clock.c | 14 #include <asm/arch/prcm.h>
|
| Makefile | 15 obj-$(CONFIG_SUN6I_PRCM) += prcm.o
|
| clock_sun8i_a83t.c | 15 #include <asm/arch/prcm.h>
|
| p2wi.c | 22 #include <asm/arch/prcm.h>
|
| /external/u-boot/arch/arm/mach-omap2/omap5/ |
| hw_data.c | 21 struct prcm_regs const **prcm = variable
386 (*prcm)->cm_l4per_clkstctrl,
387 (*prcm)->cm_l3init_clkstctrl,
388 (*prcm)->cm_memif_clkstctrl,
389 (*prcm)->cm_l4cfg_clkstctrl,
391 (*prcm)->cm_gmac_clkstctrl,
397 (*prcm)->cm_l3_gpmc_clkctrl,
398 (*prcm)->cm_memif_emif_1_clkctrl,
399 (*prcm)->cm_memif_emif_2_clkctrl,
400 (*prcm)->cm_l4cfg_l4_cfg_clkctrl
[all...] |
| Makefile | 10 obj-y += prcm-regs.o
|
| hwinit.c | 219 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
221 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
273 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
275 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
277 clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
279 writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
427 writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
429 writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
434 return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
452 rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK
[all...] |
| dra7xx_iodelay.c | 28 clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
31 (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
41 clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
45 (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
|
| /external/u-boot/arch/arm/mach-omap2/omap4/ |
| hw_data.c | 19 struct prcm_regs const **prcm = variable
331 (*prcm)->cm_l4per_clkstctrl,
332 (*prcm)->cm_l3init_clkstctrl,
333 (*prcm)->cm_memif_clkstctrl,
334 (*prcm)->cm_l4cfg_clkstctrl,
339 (*prcm)->cm_l3_gpmc_clkctrl,
340 (*prcm)->cm_memif_emif_1_clkctrl,
341 (*prcm)->cm_memif_emif_2_clkctrl,
342 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
343 (*prcm)->cm_wkup_gpio1_clkctrl
[all...] |
| Makefile | 10 obj-y += prcm-regs.o
|
| /external/u-boot/arch/arm/mach-omap2/ |
| vc.c | 77 writel(val, (*prcm)->prm_vc_cfg_i2c_clk);
85 writel(val, (*prcm)->prm_vc_cfg_i2c_mode);
111 writel(reg_val, (*prcm)->prm_vc_val_bypass);
115 (*prcm)->prm_vc_val_bypass);
119 reg_val = readl((*prcm)->prm_vc_val_bypass) &
|
| clocks-common.c | 58 ind = (readl((*prcm)->cm_sys_clksel) &
327 (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
328 bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
329 clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
331 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
339 do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
364 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
369 do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
390 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
393 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params
[all...] |
| /external/u-boot/arch/arm/mach-omap2/omap3/ |
| clock.c | 30 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
121 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
233 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
286 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
310 struct prcm *prcm_base = (struct prcm *)PRCM_BASE
[all...] |
| Makefile | 15 obj-y += prcm-regs.o
|
| board.c | 251 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
256 * We need to take care of WD2-MPU or take a PRCM reset. WD3
257 * should not be running and does not generate a PRCM reset.
|
| /external/u-boot/board/ti/omap5_uevm/ |
| evm.c | 165 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
168 setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
172 setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
176 auxclk = readl((*prcm)->scrm_auxclk1);
179 writel(auxclk, (*prcm)->scrm_auxclk1);
|
| /external/u-boot/board/compulab/cm_t54/ |
| cm_t54.c | 207 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk);
209 setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk);
214 clrbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk);
215 clrbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk);
|
| /external/u-boot/arch/arm/mach-omap2/am33xx/ |
| Makefile | 22 obj-y += prcm-regs.o
|
| /external/u-boot/board/htkw/mcx/ |
| mcx.c | 126 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
|
| /external/u-boot/arch/arm/cpu/armv7/sunxi/ |
| psci.c | 14 #include <asm/arch/prcm.h>
160 struct sunxi_prcm_reg *prcm = local
163 sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,
|
| /external/u-boot/board/compulab/common/ |
| omap3_display.c | 228 * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) /
230 * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1))
398 struct prcm *prcm = (struct prcm *)PRCM_BASE; local
421 clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
|
| /external/u-boot/board/teejet/mt_ventoux/ |
| mt_ventoux.c | 304 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
|
| /external/u-boot/drivers/usb/phy/ |
| omap_usb_phy.c | 197 setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
200 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl,
|
