/external/u-boot/arch/arm/mach-davinci/include/mach/ |
dm365_lowlevel.h | 16 int dm365_pll1_init(unsigned long pllmult, unsigned long prediv); 17 int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
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pll_defs.h | 19 unsigned int prediv; /* 0x114 */ member in struct:dv_pll_regs
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hardware.h | 401 dv_reg prediv; member in struct:davinci_pllc_regs
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/external/u-boot/arch/arm/mach-davinci/ |
dm365_lowlevel.c | 25 int dm365_pll1_init(unsigned long pllmult, unsigned long prediv) 57 writel(prediv, &dv_pll0_regs->prediv); 102 int dm365_pll2_init(unsigned long pllm, unsigned long prediv) 139 writel(prediv, &dv_pll1_regs->prediv);
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da850_lowlevel.c | 82 /* program the prediv */ 85 ®->prediv);
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/external/u-boot/drivers/video/rockchip/ |
rk_mipi.c | 193 * Mipi dphy config function. Calculate the suitable prediv, feedback div, 203 u64 prediv = 1; local 258 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz 276 prediv = i; 280 fbdiv = ddr_clk * prediv / refclk; 281 ddr_clk = refclk * fbdiv / prediv; 285 __func__, refclk, prediv, fbdiv, ddr_clk); 287 /* config prediv and feedback reg */ 288 test_data[0] = prediv - 1;
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/external/u-boot/arch/arm/mach-keystone/ |
clock.c | 281 unsigned long mult = 1, prediv = 1, output_div = 2; local 290 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1; 299 ret = ret / prediv / output_div * mult; 331 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1; 336 ret = ((ret / prediv) * mult) / output_div;
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/external/u-boot/drivers/clk/renesas/ |
clk-rcar-gen3.c | 167 u32 value, mult, div, prediv, postdiv; local 297 prediv = (value >> CPG_RPC_PREDIV_OFFSET) & 299 if (prediv == 2) 301 else if (prediv == 3) 310 debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n", 312 core->parent, prediv, postdiv, rate);
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/external/u-boot/arch/arm/mach-keystone/include/mach/ |
clock_defs.h | 20 u32 prediv; /* 14 */ member in struct:pllctl_regs
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