| /device/linaro/bootloader/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ |
| div.S | 35 rsbs r12, r1, r0, LSR #4
38 rsbs r12, r1, r0, LSR #8
55 rsbs r12, r1, r0, LSR #1
58 rsbs r12, r1, r0, LSR #4
60 rsbs r12, r1, r0, LSR #8
65 rsbs r12, r1, r0, LSR #7
68 rsbs r12, r1, r0,LSR #6
71 rsbs r12, r1, r0, LSR #5
74 rsbs r12, r1, r0, LSR #4
78 rsbs r12, r1, r0, LSR #3
[all...] |
| ldivmod.S | 34 rsbs r0,r0,#0
39 rsbs r2,r2,#0
45 rsbs r0,r0,#0
50 rsbs r2,r2,#0
|
| uldiv.S | 179 rsbs lr, lr, #0 // 0x0
|
| uldiv.asm | 178 rsbs lr, lr, #0 ; 0x0
|
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| sad_halfpel_inline.h | 58 rsbs tmp, tmp, tmp2, asr #1 ;
70 rsbs tmp, tmp2, tmp, asr #2 ;
89 asm volatile("rsbs %1, %3, %4, asr #1\n\t"
109 asm volatile("rsbs %1, %4, %3, asr #2\n\t"
|
| sad_inline.h | 181 rsbs tmp, tmp, tmp2 ;
323 RSBS x11, dmin, x10, lsr #16;
354 asm volatile("rsbs %1, %4, %3\n\t"
|
| /external/capstone/suite/MC/ARM/ |
| basic-thumb-instructions.s.cs | 88 0x63,0x42 = rsbs r3, r4, #0
95 0x59,0x42 = rsbs r1, r3, #0
|
| basic-thumb2-instructions.s.cs | 642 0xdc,0xf1,0x0f,0x03 = rsbs.w r3, r12, #15
647 0x4b,0x42 = rsbs r3, r1, #0
652 0xd1,0xeb,0x47,0x02 = rsbs r2, r1, r7, lsl #1
[all...] |
| /device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/Arm/ |
| Math64.S | 92 rsbs r2, r2, #32
118 rsbs r2, r2, #32
|
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rdlow-rnlow-operand-immediate-zero-t32.cc | 51 #define FOREACH_INSTRUCTION(M) M(rsbs)
162 #include "aarch32/traces/assembler-cond-rdlow-rnlow-operand-immediate-zero-rsbs-t32.h"
|
| test-assembler-cond-rd-rn-operand-const-a32.cc | 65 M(rsbs) \
[all...] |
| test-assembler-cond-rd-rn-operand-const-t32.cc | 67 M(rsbs) \
[all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb-instructions.s | 445 @ CHECK: rsbs r3, r4, #0 @ encoding: [0x63,0x42]
494 rsbs r1, r3, #0
496 @ CHECK: rsbs r1, r3, #0 @ encoding: [0x59,0x42]
|
| basic-arm-instructions.s | [all...] |
| diagnostics.s | 662 rsbs r7, r8, #-2149, #0
663 rsbs r7, r8, #100, #1
|
| basic-thumb2-instructions.s | [all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| basic-thumb-instructions.s | 394 @ CHECK: rsbs r3, r4, #0 @ encoding: [0x63,0x42]
443 rsbs r1, r3, #0
445 @ CHECK: rsbs r1, r3, #0 @ encoding: [0x59,0x42]
|
| basic-thumb2-instructions.s | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| basic-thumb-instructions.s | 445 @ CHECK: rsbs r3, r4, #0 @ encoding: [0x63,0x42]
494 rsbs r1, r3, #0
496 @ CHECK: rsbs r1, r3, #0 @ encoding: [0x59,0x42]
|
| basic-arm-instructions.s | [all...] |
| diagnostics.s | 743 rsbs r7, r8, #-2149, #0
744 rsbs r7, r8, #100, #1
[all...] |
| basic-thumb2-instructions.s | [all...] |
| /external/u-boot/arch/arm/lib/ |
| uldivmod.S | 178 rsbs D_0, D_0, #31
|
| /external/vixl/src/aarch32/ |
| assembler-aarch32.h | 2949 void rsbs(Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
2952 void rsbs(Condition cond, Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
2955 void rsbs(EncodingSize size, function in class:vixl::aarch32::Assembler
[all...] |
| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| assembler_arm.h | 461 void rsbs(Register rd, Register rn, Operand o, Condition cond = AL);
[all...] |
