1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010,2011 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 7 #ifndef _SCU_H_ 8 #define _SCU_H_ 9 10 /* ARM Snoop Control Unit (SCU) registers */ 11 struct scu_ctlr { 12 uint scu_ctrl; /* SCU Control Register, offset 00 */ 13 uint scu_cfg; /* SCU Config Register, offset 04 */ 14 uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */ 15 uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */ 16 uint scu_reserved0[12]; /* reserved, offset 10-3C */ 17 uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */ 18 uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */ 19 uint scu_reserved1[2]; /* reserved, offset 48-4C */ 20 uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */ 21 uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */ 22 }; 23 24 #define SCU_CTRL_ENABLE (1 << 0) 25 26 #endif /* SCU_H */ 27
