| /device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/Ipf/ |
| SetJmp.s | 36 stf.spill.nta [in0] = f2, 0x10
37 st8.spill.nta [r10] = r4, 8
40 stf.spill.nta [in0] = f3, 0x10
41 st8.spill.nta [r10] = r5, 8
44 stf.spill.nta [in0] = f4, 0x10
45 st8.spill.nta [r10] = r6, 8
48 stf.spill.nta [in0] = f5, 0x10
49 st8.spill.nta [r10] = r7, 8
52 stf.spill.nta [in0] = f16, 0x10
53 st8.spill.nta [r10] = sp, 8
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/ |
| setjmp.s | 37 stf.spill.nta [in0] = f2, 0x10
38 st8.spill.nta [r10] = r4, 8
41 stf.spill.nta [in0] = f3, 0x10
42 st8.spill.nta [r10] = r5, 8
45 stf.spill.nta [in0] = f4, 0x10
46 st8.spill.nta [r10] = r6, 8
49 stf.spill.nta [in0] = f5, 0x10
50 st8.spill.nta [r10] = r7, 8
53 stf.spill.nta [in0] = f16, 0x10
54 st8.spill.nta [r10] = sp, 8
[all...] |
| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/Ipf/ |
| IpfThunk.s | 340 stf.spill [sp]=f2,-16;; stf.spill [sp]=f3,-16;;
341 stf.spill [sp]=f4,-16;; stf.spill [sp]=f5,-16;; stf.spill [sp]=f6,-16;; stf.spill [sp]=f7,-16;;
342 stf.spill [sp]=f8,-16;; stf.spill [sp]=f9,-16;; stf.spill [sp]=f10,-16;; stf.spill [sp]=f11,-16;;
[all...] |
| /external/libunwind/src/ia64/ |
| getcontext.S | 51 st8.spill [r2] = r1, (SC_FLAGS - GR(1)) // M3
66 st8.spill [r2] = r12, (GR(4) - GR(12)) // M3
70 stf.spill [r3] = f2 // M2
71 stf.spill [r8] = f16 // M3
76 stf.spill [r9] = f24, (FR(31) - FR(24)) // M2
80 stf.spill [r9] = f31 // M2
81 st8.spill [r2] = r4, (GR(5) - GR(4)) // M3, bank 1
85 .mem.offset 0,0; st8.spill [r2] = r5, (GR(6) - GR(5)) // M4, bank 0
86 .mem.offset 8,0; st8.spill [r3] = r7, (BR(0) - GR(7)) // M3, bank 0
90 st8.spill [r2] = r6, (BR(1) - GR(6)) // M2, bank
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/Pei/PeiLib/Ipf/ |
| SetJmp.s | 79 st8.spill [r11] = r4, J_R6-J_R4
81 st8.spill [r10] = r5, J_R7-J_R5
83 st8.spill [r11] = r6, J_SP-J_R6
85 st8.spill [r10] = r7, J_F3-J_R7
87 st8.spill [r11] = sp, J_F2-J_SP
92 mov r2 = ar.unat // save Unat register after spill
100 stf.spill [r11] = f2, J_F4-J_F2
101 stf.spill [r10] = f3, J_F5-J_F3
103 stf.spill [r11] = f4, J_F16-J_F4
104 stf.spill [r10] = f5, J_F17-J_F5
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/DebugSupportDxe/Ipf/ |
| AsmFuncs.s | 734 st8.spill [in0]=r0,8;;
735 st8.spill [in0]=r1,8;; // save R1 - R31
736 st8.spill [in0]=r2,8;;
737 st8.spill [in0]=r3,8;;
738 st8.spill [in0]=r4,8;;
739 st8.spill [in0]=r5,8;;
740 st8.spill [in0]=r6,8;;
741 st8.spill [in0]=r7,8;;
742 st8.spill [in0]=r8,8;;
743 st8.spill [in0]=r9,8;;
[all...] |
| /external/llvm/lib/CodeGen/ |
| Spiller.h | 23 /// Implementations are utility classes which insert spill or remat code on
30 /// spill - Spill the LRE.getParent() live interval.
31 virtual void spill(LiveRangeEdit &LRE) = 0;
35 /// Create and return a spiller that will insert spill code directly instead
|
| RegAllocBasic.cpp | 57 /// algorithm. It prioritizes live virtual registers by spill weight and spills
163 // Spill or split all live virtual registers currently unified under PhysReg
189 // Spill each interfering vreg allocated to PhysReg or an alias.
191 LiveInterval &Spill = *Intfs[i];
194 if (!VRM->hasPhys(Spill.reg))
199 Matrix->unassign(Spill);
201 // Spill the extracted interval.
202 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, nullptr, &DeadRemats);
203 spiller().spill(LRE);
222 // Populate a list of physical register spill candidates
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| Spiller.h | 22 /// Implementations are utility classes which insert spill or remat code on
28 /// spill - Spill the LRE.getParent() live interval.
29 virtual void spill(LiveRangeEdit &LRE) = 0;
38 /// Create and return a spiller that will insert spill code directly instead
|
| Spiller.cpp | 73 /// Add spill ranges for every use/def of the live interval, inserting loads
81 "Attempting to spill already spilled value.");
84 "Trying to spill a stack slot.");
86 DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
174 /// Spills any live range using the spill-everywhere method with no attempt at
183 void spill(LiveRangeEdit &LRE) { function in class:__anon40579::TrivialSpiller
211 void spill(LiveRangeEdit &LRE) { function in class:__anon40580::StandardSpiller
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| Spiller.h | 22 /// Implementations are utility classes which insert spill or remat code on
30 /// spill - Spill the LRE.getParent() live interval.
31 virtual void spill(LiveRangeEdit &LRE) = 0;
36 /// Create and return a spiller that will insert spill code directly instead
|
| /art/compiler/utils/ |
| managed_register.h | 122 ManagedRegisterSpill spill(x);
123 std::vector<ManagedRegisterSpill>::push_back(spill);
127 ManagedRegisterSpill spill(x, size);
128 std::vector<ManagedRegisterSpill>::push_back(spill);
|
| /art/compiler/utils/x86_64/ |
| jni_macro_assembler_x86_64.cc | 47 x86_64::X86_64ManagedRegister spill = spill_regs[i].AsX86_64(); local
48 if (spill.IsCpuRegister()) {
49 __ pushq(spill.AsCpuRegister());
52 cfi().RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0);
62 // spill xmms
65 x86_64::X86_64ManagedRegister spill = spill_regs[i].AsX86_64(); local
66 if (spill.IsXmmRegister()) {
68 __ movsd(Address(CpuRegister(RSP), offset), spill.AsXmmRegister());
69 cfi().RelOffset(DWARFReg(spill.AsXmmRegister().AsFloatRegister()), offset);
78 for (const ManagedRegisterSpill& spill : entry_spills)
112 x86_64::X86_64ManagedRegister spill = spill_regs[i].AsX86_64(); local
125 x86_64::X86_64ManagedRegister spill = spill_regs[i].AsX86_64(); local
[all...] |
| /art/runtime/arch/arm/ |
| jni_entrypoints_arm.S | 24 push {r0, r1, r2, r3, lr} @ spill regs
|
| /external/libffi/src/ia64/ |
| unix.S | 304 /* Spill all of the possible argument registers. */
308 stf.spill [r16] = f8, 32
309 stf.spill [r17] = f9, 32
312 stf.spill [r16] = f10, 32
313 stf.spill [r17] = f11, 32
315 stf.spill [r16] = f12, 32
316 stf.spill [r17] = f13, 32
318 stf.spill [r16] = f14, 32
319 stf.spill [r17] = f15, 24
322 st8.spill [r16] = in0, 1
[all...] |
| /external/python/cpython2/Modules/_ctypes/libffi/src/ia64/ |
| unix.S | 304 /* Spill all of the possible argument registers. */
308 stf.spill [r16] = f8, 32
309 stf.spill [r17] = f9, 32
312 stf.spill [r16] = f10, 32
313 stf.spill [r17] = f11, 32
315 stf.spill [r16] = f12, 32
316 stf.spill [r17] = f13, 32
318 stf.spill [r16] = f14, 32
319 stf.spill [r17] = f15, 24
322 st8.spill [r16] = in0, 1
[all...] |
| /art/compiler/utils/x86/ |
| jni_macro_assembler_x86.cc | 53 Register spill = spill_regs[i].AsX86().AsCpuRegister(); local
54 __ pushl(spill);
57 cfi().RelOffset(DWARFReg(spill), 0);
70 for (const ManagedRegisterSpill& spill : entry_spills) {
71 if (spill.AsX86().IsCpuRegister()) {
72 int offset = frame_size + spill.getSpillOffset();
73 __ movl(Address(ESP, offset), spill.AsX86().AsCpuRegister());
75 DCHECK(spill.AsX86().IsXmmRegister());
76 if (spill.getSize() == 8) {
77 __ movsd(Address(ESP, frame_size + spill.getSpillOffset()), spill.AsX86().AsXmmRegister())
96 Register spill = spill_regs[i].AsX86().AsCpuRegister(); local
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86CompilationCallback_Win64.asm | 24 ; WARNING: We cannot use register spill area - we're generating stubs by hands!
33 ; Save all XMM arg registers. Also allocate reg spill area.
|
| /device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/X64/ |
| SwitchStack.asm | 45 ; in case the callee wishes to spill them.
|
| SwitchStack.S | 48 # in case the callee wishes to spill them.
|
| /device/linaro/bootloader/edk2/EmulatorPkg/Sec/X64/ |
| SwitchRam.asm | 49 sub rsp, 028h ; Allocate register spill area & 16-byte align stack
67 sub rsp, 028h ; Allocate register spill area & 16-byte align stack
|
| /device/linaro/bootloader/edk2/EmulatorPkg/Unix/Host/X64/ |
| SwitchStack.S | 47 # in case the callee wishes to spill them.
|
| /external/libunwind/tests/ |
| ia64-test-nat-asm.S | 108 stf.spill [sp] = f2, -16
172 /* Spill r4 into memory and then save r5 in r4. */
188 st8.spill [sp] = r4, -16
209 /* Spill r6 into memory and save primary ar.unat in a register. */
225 st8.spill [sp] = r6, -16;;
246 /* Spill r6 into memory and save primary ar.unat in memory. */
263 st8.spill [sp] = r6, -16;;
287 /* Spill r6 into memory and save primary ar.unat in register,
305 st8.spill [sp] = r6, -16;;
330 /* Spill r6 into memory and save primary ar.unat in register
[all...] |
| /art/compiler/jni/quick/x86/ |
| calling_convention_x86.cc | 153 // We spill the argument registers on X86 to free them up for scratch use, we then assume
163 ManagedRegisterSpill spill(in_reg, size, spill_offset);
164 entry_spills_.push_back(spill);
169 // We have to spill the second half of the long.
236 // Plus return value spill area size
|
| /art/compiler/jni/quick/x86_64/ |
| calling_convention_x86_64.cc | 158 // We spill the argument registers on X86 to free them up for scratch use, we then assume
167 ManagedRegisterSpill spill(in_reg, size, spill_offset);
168 entry_spills_.push_back(spill);
218 // Plus return value spill area size
|
