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  /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
mrc.h 78 // tCL is DRAM CAS Latency in clocks.
83 uint8_t tCL; // CAS latency in clocks
gen5_iosf_sb_definitions.h 82 uint32_t tCL :3; /**< bit [14:12] CAS Latency */
meminit.c 393 uint8_t TCL, WL;
415 TCL = mrc_params->params.tCL; // CAS latency in clocks
416 TRP = TCL; // Per CAT MRC
417 TRCD = TCL; // Per CAT MRC
430 Dtr0.field.tCL = TCL - 5; //Convert from TCL (DRAM clocks) to VLV indx
452 Dtr3.field.tRWSR = TCL - 5 + 1;
457 Dtr3.field.tRWSR = TCL - 5 + 1;
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  /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
DdrMemoryController.h 184 unsigned tCL :2; /**< CAS Latency (3,4,5,6) */
  /device/linaro/bootloader/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/
MrcWrapper.h 123 UINT8 tCL; ///< DRAM CAS Latency in clocks.
MrcWrapper.c 133 MrcData->params.tCL = ItemData->tCL;
152 DEBUG ((EFI_D_INFO, "MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n",
154 MrcData->params.tCL,
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