| /external/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| ddr2_v3s.c | 34 u8 tcwl = 3; /* CWL 6 */ local
43 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
59 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
|
| lpddr3_stock.c | 34 u8 tcwl = 3; /* CWL 6 */ local
43 u8 twtp = tcwl + 4 + twr + 1;
44 u8 twr2rd = tcwl + 4 + 1 + twtr;
45 u8 trd2wr = tcl + 4 + 5 - tcwl + 1;
58 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
|
| ddr3_1333.c | 34 u8 tcwl = 4; /* CWL 8 */ local
43 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
62 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
|
| /external/u-boot/arch/arm/mach-sunxi/ |
| dram_sun8i_a83t.c | 117 u8 tcwl = 4; /* CWL 8 */ local
126 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
127 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
128 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
159 tcwl = 3; /* CWL 8 */
165 twtp = tcwl + 4 + twr + 1; /* CWL + BL/2 + tWR */
166 twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */
167 trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */
174 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
|
| dram_sun8i_a33.c | 117 u8 tcwl = 4; /* CWL 8 */ local
126 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
127 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
128 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
142 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
|
| dram_sun6i.c | 214 writel(MCTL_TCWL, &mctl_ctl->tcwl);
|
| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| sdram.h | 55 u32 tcwl; member in struct:rk3288_sdram_pctl_timing
|
| sdram_rk3036.h | 52 u32 tcwl; member in struct:rk3036_ddr_pctl
249 u32 tcwl; member in struct:rk3036_pctl_timing
|
| sdram_rk322x.h | 88 u32 tcwl; member in struct:rk322x_ddr_pctl
214 u32 tcwl; member in struct:rk322x_pctl_timing
|
| ddr_rk3368.h | 56 u32 tcwl; member in struct:rk3368_ddr_pctl
|
| ddr_rk3288.h | 51 u32 tcwl; member in struct:rk3288_ddr_pctl
|
| /external/u-boot/drivers/ram/rockchip/ |
| dmc-rk3368.c | 155 u32 tcl, u32 tal, u32 tcwl)
165 clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
241 mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
473 pctl_timing->tcwl = 10;
476 pctl_timing->tcwl = 6;
479 pctl_timing->tcwl = 7;
482 pctl_timing->tcwl = 8;
493 pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
560 writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
832 params->pctl_timing.tcwl);
[all...] |
| sdram_rk322x.c | 430 writel((readl(&pctl->tcwl) - 1) / 2 - 1, &pctl->dfitphywrlat);
444 writel(readl(&pctl->tcwl) / 2 - 1, &pctl->dfitphywrlat);
497 writel(pctl_timing->tcwl, &ddr_phy->ddrphy_reg[0xc]);
|
| sdram_rk3288.c | 252 writel(sdram_params->pctl_timing.tcwl,
273 writel(sdram_params->pctl_timing.tcwl - 1,
|
| sdram_rk3188.c | 241 writel(sdram_params->pctl_timing.tcwl - 1,
|
| /external/u-boot/arch/arm/mach-imx/mx6/ |
| ddr.c | 1229 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; local
[all...] |
| /external/u-boot/arch/arm/include/asm/arch-sunxi/ |
| dram_sun6i.h | 79 u32 tcwl; /* 0xec */ member in struct:sunxi_mctl_ctl_reg
|
| /external/u-boot/arch/arm/mach-rockchip/rk3036/ |
| sdram_rk3036.c | 612 reg = readl(&pctl->tcwl);
|
