1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2007, 2010 Freescale Semiconductor, Inc. 4 * 5 * Author: Roy Zang <tie-fei.zang (at) freescale.com>, Sep, 2007 6 * 7 * Description: 8 * ULI 526x Ethernet port driver. 9 * Based on the Linux driver: drivers/net/tulip/uli526x.c 10 */ 11 12 #include <common.h> 13 #include <malloc.h> 14 #include <net.h> 15 #include <netdev.h> 16 #include <asm/io.h> 17 #include <pci.h> 18 #include <miiphy.h> 19 20 /* some kernel function compatible define */ 21 22 #undef DEBUG 23 24 /* Board/System/Debug information/definition */ 25 #define ULI_VENDOR_ID 0x10B9 26 #define ULI5261_DEVICE_ID 0x5261 27 #define ULI5263_DEVICE_ID 0x5263 28 /* ULi M5261 ID*/ 29 #define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID) 30 /* ULi M5263 ID*/ 31 #define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID) 32 33 #define ULI526X_IO_SIZE 0x100 34 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */ 35 #define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */ 36 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */ 37 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */ 38 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT) 39 #define TX_BUF_ALLOC 0x300 40 #define RX_ALLOC_SIZE PKTSIZE 41 #define ULI526X_RESET 1 42 #define CR0_DEFAULT 0 43 #define CR6_DEFAULT 0x22200000 44 #define CR7_DEFAULT 0x180c1 45 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */ 46 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */ 47 #define MAX_PACKET_SIZE 1514 48 #define ULI5261_MAX_MULTICAST 14 49 #define RX_COPY_SIZE 100 50 #define MAX_CHECK_PACKET 0x8000 51 52 #define ULI526X_10MHF 0 53 #define ULI526X_100MHF 1 54 #define ULI526X_10MFD 4 55 #define ULI526X_100MFD 5 56 #define ULI526X_AUTO 8 57 58 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */ 59 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */ 60 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */ 61 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */ 62 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */ 63 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */ 64 65 /* CR9 definition: SROM/MII */ 66 #define CR9_SROM_READ 0x4800 67 #define CR9_SRCS 0x1 68 #define CR9_SRCLK 0x2 69 #define CR9_CRDOUT 0x8 70 #define SROM_DATA_0 0x0 71 #define SROM_DATA_1 0x4 72 #define PHY_DATA_1 0x20000 73 #define PHY_DATA_0 0x00000 74 #define MDCLKH 0x10000 75 76 #define PHY_POWER_DOWN 0x800 77 78 #define SROM_V41_CODE 0x14 79 80 #define SROM_CLK_WRITE(data, ioaddr) do { \ 81 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \ 82 udelay(5); \ 83 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \ 84 udelay(5); \ 85 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \ 86 udelay(5); \ 87 } while (0) 88 89 /* Structure/enum declaration */ 90 91 struct tx_desc { 92 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */ 93 char *tx_buf_ptr; /* Data for us */ 94 struct tx_desc *next_tx_desc; 95 }; 96 97 struct rx_desc { 98 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */ 99 char *rx_buf_ptr; /* Data for us */ 100 struct rx_desc *next_rx_desc; 101 }; 102 103 struct uli526x_board_info { 104 u32 chip_id; /* Chip vendor/Device ID */ 105 pci_dev_t pdev; 106 107 long ioaddr; /* I/O base address */ 108 u32 cr0_data; 109 u32 cr5_data; 110 u32 cr6_data; 111 u32 cr7_data; 112 u32 cr15_data; 113 114 /* pointer for memory physical address */ 115 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */ 116 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */ 117 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */ 118 dma_addr_t first_tx_desc_dma; 119 dma_addr_t first_rx_desc_dma; 120 121 /* descriptor pointer */ 122 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */ 123 unsigned char *buf_pool_start; /* Tx buffer pool align dword */ 124 unsigned char *desc_pool_ptr; /* descriptor pool memory */ 125 struct tx_desc *first_tx_desc; 126 struct tx_desc *tx_insert_ptr; 127 struct tx_desc *tx_remove_ptr; 128 struct rx_desc *first_rx_desc; 129 struct rx_desc *rx_ready_ptr; /* packet come pointer */ 130 unsigned long tx_packet_cnt; /* transmitted packet count */ 131 132 u16 PHY_reg4; /* Saved Phyxcer register 4 value */ 133 134 u8 media_mode; /* user specify media mode */ 135 u8 op_mode; /* real work dedia mode */ 136 u8 phy_addr; 137 138 /* NIC SROM data */ 139 unsigned char srom[128]; 140 }; 141 142 enum uli526x_offsets { 143 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, 144 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, 145 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70, 146 DCR15 = 0x78 147 }; 148 149 enum uli526x_CR6_bits { 150 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, 151 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, 152 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000 153 }; 154 155 /* Global variable declaration -- */ 156 157 static unsigned char uli526x_media_mode = ULI526X_AUTO; 158 159 static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20] 160 __attribute__ ((aligned(32))); 161 static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4]; 162 163 /* For module input parameter */ 164 static int mode = 8; 165 166 /* function declaration -- */ 167 static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length); 168 static u16 read_srom_word(long, int); 169 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long); 170 static void allocate_rx_buffer(struct uli526x_board_info *); 171 static void update_cr6(u32, unsigned long); 172 static u16 uli_phy_read(unsigned long, u8, u8, u32); 173 static u16 phy_readby_cr10(unsigned long, u8, u8); 174 static void uli_phy_write(unsigned long, u8, u8, u16, u32); 175 static void phy_writeby_cr10(unsigned long, u8, u8, u16); 176 static void phy_write_1bit(unsigned long, u32, u32); 177 static u16 phy_read_1bit(unsigned long, u32); 178 static int uli526x_rx_packet(struct eth_device *); 179 static void uli526x_free_tx_pkt(struct eth_device *, 180 struct uli526x_board_info *); 181 static void uli526x_reuse_buf(struct rx_desc *); 182 static void uli526x_init(struct eth_device *); 183 static void uli526x_set_phyxcer(struct uli526x_board_info *); 184 185 186 static int uli526x_init_one(struct eth_device *, bd_t *); 187 static void uli526x_disable(struct eth_device *); 188 static void set_mac_addr(struct eth_device *); 189 190 static struct pci_device_id uli526x_pci_tbl[] = { 191 { ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */ 192 { ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */ 193 {} 194 }; 195 196 /* ULI526X network board routine */ 197 198 /* 199 * Search ULI526X board, register it 200 */ 201 202 int uli526x_initialize(bd_t *bis) 203 { 204 pci_dev_t devno; 205 int card_number = 0; 206 struct eth_device *dev; 207 struct uli526x_board_info *db; /* board information structure */ 208 209 u32 iobase; 210 int idx = 0; 211 212 while (1) { 213 /* Find PCI device */ 214 devno = pci_find_devices(uli526x_pci_tbl, idx++); 215 if (devno < 0) 216 break; 217 218 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); 219 iobase &= ~0xf; 220 221 dev = (struct eth_device *)malloc(sizeof *dev); 222 if (!dev) { 223 printf("uli526x: Can not allocate memory\n"); 224 break; 225 } 226 memset(dev, 0, sizeof(*dev)); 227 sprintf(dev->name, "uli526x#%d", card_number); 228 db = (struct uli526x_board_info *) 229 malloc(sizeof(struct uli526x_board_info)); 230 231 dev->priv = db; 232 db->pdev = devno; 233 dev->iobase = iobase; 234 235 dev->init = uli526x_init_one; 236 dev->halt = uli526x_disable; 237 dev->send = uli526x_start_xmit; 238 dev->recv = uli526x_rx_packet; 239 240 /* init db */ 241 db->ioaddr = dev->iobase; 242 /* get chip id */ 243 244 pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id); 245 #ifdef DEBUG 246 printf("uli526x: uli526x @0x%x\n", iobase); 247 printf("uli526x: chip_id%x\n", db->chip_id); 248 #endif 249 eth_register(dev); 250 card_number++; 251 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); 252 udelay(10 * 1000); 253 } 254 return card_number; 255 } 256 257 static int uli526x_init_one(struct eth_device *dev, bd_t *bis) 258 { 259 260 struct uli526x_board_info *db = dev->priv; 261 int i; 262 263 switch (mode) { 264 case ULI526X_10MHF: 265 case ULI526X_100MHF: 266 case ULI526X_10MFD: 267 case ULI526X_100MFD: 268 uli526x_media_mode = mode; 269 break; 270 default: 271 uli526x_media_mode = ULI526X_AUTO; 272 break; 273 } 274 275 /* Allocate Tx/Rx descriptor memory */ 276 db->desc_pool_ptr = (uchar *)&desc_pool_array[0]; 277 db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0]; 278 if (db->desc_pool_ptr == NULL) 279 return -1; 280 281 db->buf_pool_ptr = (uchar *)&buf_pool[0]; 282 db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0]; 283 if (db->buf_pool_ptr == NULL) 284 return -1; 285 286 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; 287 db->first_tx_desc_dma = db->desc_pool_dma_ptr; 288 289 db->buf_pool_start = db->buf_pool_ptr; 290 db->buf_pool_dma_start = db->buf_pool_dma_ptr; 291 292 #ifdef DEBUG 293 printf("%s(): db->ioaddr= 0x%x\n", 294 __FUNCTION__, db->ioaddr); 295 printf("%s(): media_mode= 0x%x\n", 296 __FUNCTION__, uli526x_media_mode); 297 printf("%s(): db->desc_pool_ptr= 0x%x\n", 298 __FUNCTION__, db->desc_pool_ptr); 299 printf("%s(): db->desc_pool_dma_ptr= 0x%x\n", 300 __FUNCTION__, db->desc_pool_dma_ptr); 301 printf("%s(): db->buf_pool_ptr= 0x%x\n", 302 __FUNCTION__, db->buf_pool_ptr); 303 printf("%s(): db->buf_pool_dma_ptr= 0x%x\n", 304 __FUNCTION__, db->buf_pool_dma_ptr); 305 #endif 306 307 /* read 64 word srom data */ 308 for (i = 0; i < 64; i++) 309 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, 310 i)); 311 312 /* Set Node address */ 313 if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) || 314 ((db->srom[0] == 0x00) && (db->srom[1] == 0x00))) 315 /* SROM absent, so write MAC address to ID Table */ 316 set_mac_addr(dev); 317 else { /*Exist SROM*/ 318 for (i = 0; i < 6; i++) 319 dev->enetaddr[i] = db->srom[20 + i]; 320 } 321 #ifdef DEBUG 322 for (i = 0; i < 6; i++) 323 printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]); 324 #endif 325 db->PHY_reg4 = 0x1e0; 326 327 /* system variable init */ 328 db->cr6_data = CR6_DEFAULT ; 329 db->cr6_data |= ULI526X_TXTH_256; 330 db->cr0_data = CR0_DEFAULT; 331 uli526x_init(dev); 332 return 0; 333 } 334 335 static void uli526x_disable(struct eth_device *dev) 336 { 337 #ifdef DEBUG 338 printf("uli526x_disable\n"); 339 #endif 340 struct uli526x_board_info *db = dev->priv; 341 342 if (!((inl(db->ioaddr + DCR12)) & 0x8)) { 343 /* Reset & stop ULI526X board */ 344 outl(ULI526X_RESET, db->ioaddr + DCR0); 345 udelay(5); 346 uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); 347 348 /* reset the board */ 349 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */ 350 update_cr6(db->cr6_data, dev->iobase); 351 outl(0, dev->iobase + DCR7); /* Disable Interrupt */ 352 outl(inl(dev->iobase + DCR5), dev->iobase + DCR5); 353 } 354 } 355 356 /* Initialize ULI526X board 357 * Reset ULI526X board 358 * Initialize TX/Rx descriptor chain structure 359 * Send the set-up frame 360 * Enable Tx/Rx machine 361 */ 362 363 static void uli526x_init(struct eth_device *dev) 364 { 365 366 struct uli526x_board_info *db = dev->priv; 367 u8 phy_tmp; 368 u16 phy_value; 369 u16 phy_reg_reset; 370 371 /* Reset M526x MAC controller */ 372 outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */ 373 udelay(100); 374 outl(db->cr0_data, db->ioaddr + DCR0); 375 udelay(5); 376 377 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */ 378 db->phy_addr = 1; 379 db->tx_packet_cnt = 0; 380 for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) { 381 /* peer add */ 382 phy_value = uli_phy_read(db->ioaddr, phy_tmp, 3, db->chip_id); 383 if (phy_value != 0xffff && phy_value != 0) { 384 db->phy_addr = phy_tmp; 385 break; 386 } 387 } 388 389 #ifdef DEBUG 390 printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr); 391 printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr); 392 #endif 393 if (phy_tmp == 32) 394 printf("Can not find the phy address!!!"); 395 396 /* Parser SROM and media mode */ 397 db->media_mode = uli526x_media_mode; 398 399 if (!(inl(db->ioaddr + DCR12) & 0x8)) { 400 /* Phyxcer capability setting */ 401 phy_reg_reset = uli_phy_read(db->ioaddr, 402 db->phy_addr, 0, db->chip_id); 403 phy_reg_reset = (phy_reg_reset | 0x8000); 404 uli_phy_write(db->ioaddr, db->phy_addr, 0, 405 phy_reg_reset, db->chip_id); 406 udelay(500); 407 408 /* Process Phyxcer Media Mode */ 409 uli526x_set_phyxcer(db); 410 } 411 /* Media Mode Process */ 412 if (!(db->media_mode & ULI526X_AUTO)) 413 db->op_mode = db->media_mode; /* Force Mode */ 414 415 /* Initialize Transmit/Receive decriptor and CR3/4 */ 416 uli526x_descriptor_init(db, db->ioaddr); 417 418 /* Init CR6 to program M526X operation */ 419 update_cr6(db->cr6_data, db->ioaddr); 420 421 /* Init CR7, interrupt active bit */ 422 db->cr7_data = CR7_DEFAULT; 423 outl(db->cr7_data, db->ioaddr + DCR7); 424 425 /* Init CR15, Tx jabber and Rx watchdog timer */ 426 outl(db->cr15_data, db->ioaddr + DCR15); 427 428 /* Enable ULI526X Tx/Rx function */ 429 db->cr6_data |= CR6_RXSC | CR6_TXSC; 430 update_cr6(db->cr6_data, db->ioaddr); 431 while (!(inl(db->ioaddr + DCR12) & 0x8)) 432 udelay(10); 433 } 434 435 /* 436 * Hardware start transmission. 437 * Send a packet to media from the upper layer. 438 */ 439 440 static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length) 441 { 442 struct uli526x_board_info *db = dev->priv; 443 struct tx_desc *txptr; 444 unsigned int len = length; 445 /* Too large packet check */ 446 if (len > MAX_PACKET_SIZE) { 447 printf(": big packet = %d\n", len); 448 return 0; 449 } 450 451 /* No Tx resource check, it never happen nromally */ 452 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) { 453 printf("No Tx resource %ld\n", db->tx_packet_cnt); 454 return 0; 455 } 456 457 /* Disable NIC interrupt */ 458 outl(0, dev->iobase + DCR7); 459 460 /* transmit this packet */ 461 txptr = db->tx_insert_ptr; 462 memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length); 463 txptr->tdes1 = cpu_to_le32(0xe1000000 | length); 464 465 /* Point to next transmit free descriptor */ 466 db->tx_insert_ptr = txptr->next_tx_desc; 467 468 /* Transmit Packet Process */ 469 if ((db->tx_packet_cnt < TX_DESC_CNT)) { 470 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ 471 db->tx_packet_cnt++; /* Ready to send */ 472 outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */ 473 } 474 475 /* Got ULI526X status */ 476 db->cr5_data = inl(db->ioaddr + DCR5); 477 outl(db->cr5_data, db->ioaddr + DCR5); 478 479 #ifdef TX_DEBUG 480 printf("%s(): length = 0x%x\n", __FUNCTION__, length); 481 printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data); 482 #endif 483 484 outl(db->cr7_data, dev->iobase + DCR7); 485 uli526x_free_tx_pkt(dev, db); 486 487 return length; 488 } 489 490 /* 491 * Free TX resource after TX complete 492 */ 493 494 static void uli526x_free_tx_pkt(struct eth_device *dev, 495 struct uli526x_board_info *db) 496 { 497 struct tx_desc *txptr; 498 u32 tdes0; 499 500 txptr = db->tx_remove_ptr; 501 while (db->tx_packet_cnt) { 502 tdes0 = le32_to_cpu(txptr->tdes0); 503 /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */ 504 if (tdes0 & 0x80000000) 505 break; 506 507 /* A packet sent completed */ 508 db->tx_packet_cnt--; 509 510 if (tdes0 != 0x7fffffff) { 511 #ifdef TX_DEBUG 512 printf("%s()tdes0=%x\n", __FUNCTION__, tdes0); 513 #endif 514 if (tdes0 & TDES0_ERR_MASK) { 515 if (tdes0 & 0x0002) { /* UnderRun */ 516 if (!(db->cr6_data & CR6_SFT)) { 517 db->cr6_data = db->cr6_data | 518 CR6_SFT; 519 update_cr6(db->cr6_data, 520 db->ioaddr); 521 } 522 } 523 } 524 } 525 526 txptr = txptr->next_tx_desc; 527 }/* End of while */ 528 529 /* Update TX remove pointer to next */ 530 db->tx_remove_ptr = txptr; 531 } 532 533 534 /* 535 * Receive the come packet and pass to upper layer 536 */ 537 538 static int uli526x_rx_packet(struct eth_device *dev) 539 { 540 struct uli526x_board_info *db = dev->priv; 541 struct rx_desc *rxptr; 542 int rxlen = 0; 543 u32 rdes0; 544 545 rxptr = db->rx_ready_ptr; 546 547 rdes0 = le32_to_cpu(rxptr->rdes0); 548 #ifdef RX_DEBUG 549 printf("%s(): rxptr->rdes0=%x\n", __FUNCTION__, rxptr->rdes0); 550 #endif 551 if (!(rdes0 & 0x80000000)) { /* packet owner check */ 552 if ((rdes0 & 0x300) != 0x300) { 553 /* A packet without First/Last flag */ 554 /* reuse this buf */ 555 printf("A packet without First/Last flag"); 556 uli526x_reuse_buf(rxptr); 557 } else { 558 /* A packet with First/Last flag */ 559 rxlen = ((rdes0 >> 16) & 0x3fff) - 4; 560 #ifdef RX_DEBUG 561 printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen); 562 #endif 563 /* error summary bit check */ 564 if (rdes0 & 0x8000) { 565 /* This is a error packet */ 566 printf("Error: rdes0: %x\n", rdes0); 567 } 568 569 if (!(rdes0 & 0x8000) || 570 ((db->cr6_data & CR6_PM) && (rxlen > 6))) { 571 572 #ifdef RX_DEBUG 573 printf("%s(): rx_skb_ptr =%x\n", 574 __FUNCTION__, rxptr->rx_buf_ptr); 575 printf("%s(): rxlen =%x\n", 576 __FUNCTION__, rxlen); 577 578 printf("%s(): buf addr =%x\n", 579 __FUNCTION__, rxptr->rx_buf_ptr); 580 printf("%s(): rxlen =%x\n", 581 __FUNCTION__, rxlen); 582 int i; 583 for (i = 0; i < 0x20; i++) 584 printf("%s(): data[%x] =%x\n", 585 __FUNCTION__, i, rxptr->rx_buf_ptr[i]); 586 #endif 587 588 net_process_received_packet( 589 (uchar *)rxptr->rx_buf_ptr, rxlen); 590 uli526x_reuse_buf(rxptr); 591 592 } else { 593 /* Reuse SKB buffer when the packet is error */ 594 printf("Reuse buffer, rdes0"); 595 uli526x_reuse_buf(rxptr); 596 } 597 } 598 599 rxptr = rxptr->next_rx_desc; 600 } 601 602 db->rx_ready_ptr = rxptr; 603 return rxlen; 604 } 605 606 /* 607 * Reuse the RX buffer 608 */ 609 610 static void uli526x_reuse_buf(struct rx_desc *rxptr) 611 { 612 613 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) 614 rxptr->rdes0 = cpu_to_le32(0x80000000); 615 else 616 printf("Buffer reuse method error"); 617 } 618 /* 619 * Initialize transmit/Receive descriptor 620 * Using Chain structure, and allocate Tx/Rx buffer 621 */ 622 623 static void uli526x_descriptor_init(struct uli526x_board_info *db, 624 unsigned long ioaddr) 625 { 626 struct tx_desc *tmp_tx; 627 struct rx_desc *tmp_rx; 628 unsigned char *tmp_buf; 629 dma_addr_t tmp_tx_dma, tmp_rx_dma; 630 dma_addr_t tmp_buf_dma; 631 int i; 632 /* tx descriptor start pointer */ 633 db->tx_insert_ptr = db->first_tx_desc; 634 db->tx_remove_ptr = db->first_tx_desc; 635 636 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */ 637 638 /* rx descriptor start pointer */ 639 db->first_rx_desc = (void *)db->first_tx_desc + 640 sizeof(struct tx_desc) * TX_DESC_CNT; 641 db->first_rx_desc_dma = db->first_tx_desc_dma + 642 sizeof(struct tx_desc) * TX_DESC_CNT; 643 db->rx_ready_ptr = db->first_rx_desc; 644 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */ 645 #ifdef DEBUG 646 printf("%s(): db->first_tx_desc= 0x%x\n", 647 __FUNCTION__, db->first_tx_desc); 648 printf("%s(): db->first_rx_desc_dma= 0x%x\n", 649 __FUNCTION__, db->first_rx_desc_dma); 650 #endif 651 /* Init Transmit chain */ 652 tmp_buf = db->buf_pool_start; 653 tmp_buf_dma = db->buf_pool_dma_start; 654 tmp_tx_dma = db->first_tx_desc_dma; 655 for (tmp_tx = db->first_tx_desc, i = 0; 656 i < TX_DESC_CNT; i++, tmp_tx++) { 657 tmp_tx->tx_buf_ptr = (char *)tmp_buf; 658 tmp_tx->tdes0 = cpu_to_le32(0); 659 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */ 660 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma); 661 tmp_tx_dma += sizeof(struct tx_desc); 662 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma); 663 tmp_tx->next_tx_desc = tmp_tx + 1; 664 tmp_buf = tmp_buf + TX_BUF_ALLOC; 665 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC; 666 } 667 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma); 668 tmp_tx->next_tx_desc = db->first_tx_desc; 669 670 /* Init Receive descriptor chain */ 671 tmp_rx_dma = db->first_rx_desc_dma; 672 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; 673 i++, tmp_rx++) { 674 tmp_rx->rdes0 = cpu_to_le32(0); 675 tmp_rx->rdes1 = cpu_to_le32(0x01000600); 676 tmp_rx_dma += sizeof(struct rx_desc); 677 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma); 678 tmp_rx->next_rx_desc = tmp_rx + 1; 679 } 680 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma); 681 tmp_rx->next_rx_desc = db->first_rx_desc; 682 683 /* pre-allocate Rx buffer */ 684 allocate_rx_buffer(db); 685 } 686 687 /* 688 * Update CR6 value 689 * Firstly stop ULI526X, then written value and start 690 */ 691 692 static void update_cr6(u32 cr6_data, unsigned long ioaddr) 693 { 694 695 outl(cr6_data, ioaddr + DCR6); 696 udelay(5); 697 } 698 699 /* 700 * Allocate rx buffer, 701 */ 702 703 static void allocate_rx_buffer(struct uli526x_board_info *db) 704 { 705 int index; 706 struct rx_desc *rxptr; 707 rxptr = db->first_rx_desc; 708 u32 addr; 709 710 for (index = 0; index < RX_DESC_CNT; index++) { 711 addr = (u32)net_rx_packets[index]; 712 addr += (16 - (addr & 15)); 713 rxptr->rx_buf_ptr = (char *) addr; 714 rxptr->rdes2 = cpu_to_le32(addr); 715 rxptr->rdes0 = cpu_to_le32(0x80000000); 716 #ifdef DEBUG 717 printf("%s(): Number 0x%x:\n", __FUNCTION__, index); 718 printf("%s(): addr 0x%x:\n", __FUNCTION__, addr); 719 printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr); 720 printf("%s(): rxptr buf address = 0x%x\n", \ 721 __FUNCTION__, rxptr->rx_buf_ptr); 722 printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2); 723 #endif 724 rxptr = rxptr->next_rx_desc; 725 } 726 } 727 728 /* 729 * Read one word data from the serial ROM 730 */ 731 732 static u16 read_srom_word(long ioaddr, int offset) 733 { 734 int i; 735 u16 srom_data = 0; 736 long cr9_ioaddr = ioaddr + DCR9; 737 738 outl(CR9_SROM_READ, cr9_ioaddr); 739 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); 740 741 /* Send the Read Command 110b */ 742 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); 743 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); 744 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr); 745 746 /* Send the offset */ 747 for (i = 5; i >= 0; i--) { 748 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0; 749 SROM_CLK_WRITE(srom_data, cr9_ioaddr); 750 } 751 752 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); 753 754 for (i = 16; i > 0; i--) { 755 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr); 756 udelay(5); 757 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) 758 ? 1 : 0); 759 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); 760 udelay(5); 761 } 762 763 outl(CR9_SROM_READ, cr9_ioaddr); 764 return srom_data; 765 } 766 767 /* 768 * Set 10/100 phyxcer capability 769 * AUTO mode : phyxcer register4 is NIC capability 770 * Force mode: phyxcer register4 is the force media 771 */ 772 773 static void uli526x_set_phyxcer(struct uli526x_board_info *db) 774 { 775 u16 phy_reg; 776 777 /* Phyxcer capability setting */ 778 phy_reg = uli_phy_read(db->ioaddr, 779 db->phy_addr, 4, db->chip_id) & ~0x01e0; 780 781 if (db->media_mode & ULI526X_AUTO) { 782 /* AUTO Mode */ 783 phy_reg |= db->PHY_reg4; 784 } else { 785 /* Force Mode */ 786 switch (db->media_mode) { 787 case ULI526X_10MHF: phy_reg |= 0x20; break; 788 case ULI526X_10MFD: phy_reg |= 0x40; break; 789 case ULI526X_100MHF: phy_reg |= 0x80; break; 790 case ULI526X_100MFD: phy_reg |= 0x100; break; 791 } 792 793 } 794 795 /* Write new capability to Phyxcer Reg4 */ 796 if (!(phy_reg & 0x01e0)) { 797 phy_reg |= db->PHY_reg4; 798 db->media_mode |= ULI526X_AUTO; 799 } 800 uli_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id); 801 802 /* Restart Auto-Negotiation */ 803 uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); 804 udelay(50); 805 } 806 807 /* 808 * Write a word to Phy register 809 */ 810 811 static void uli_phy_write(unsigned long iobase, u8 phy_addr, u8 offset, 812 u16 phy_data, u32 chip_id) 813 { 814 u16 i; 815 unsigned long ioaddr; 816 817 if (chip_id == PCI_ULI5263_ID) { 818 phy_writeby_cr10(iobase, phy_addr, offset, phy_data); 819 return; 820 } 821 /* M5261/M5263 Chip */ 822 ioaddr = iobase + DCR9; 823 824 /* Send 33 synchronization clock to Phy controller */ 825 for (i = 0; i < 35; i++) 826 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 827 828 /* Send start command(01) to Phy */ 829 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); 830 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 831 832 /* Send write command(01) to Phy */ 833 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); 834 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 835 836 /* Send Phy address */ 837 for (i = 0x10; i > 0; i = i >> 1) 838 phy_write_1bit(ioaddr, phy_addr & i ? 839 PHY_DATA_1 : PHY_DATA_0, chip_id); 840 841 /* Send register address */ 842 for (i = 0x10; i > 0; i = i >> 1) 843 phy_write_1bit(ioaddr, offset & i ? 844 PHY_DATA_1 : PHY_DATA_0, chip_id); 845 846 /* written trasnition */ 847 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 848 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); 849 850 /* Write a word data to PHY controller */ 851 for (i = 0x8000; i > 0; i >>= 1) 852 phy_write_1bit(ioaddr, phy_data & i ? 853 PHY_DATA_1 : PHY_DATA_0, chip_id); 854 } 855 856 /* 857 * Read a word data from phy register 858 */ 859 860 static u16 uli_phy_read(unsigned long iobase, u8 phy_addr, u8 offset, 861 u32 chip_id) 862 { 863 int i; 864 u16 phy_data; 865 unsigned long ioaddr; 866 867 if (chip_id == PCI_ULI5263_ID) 868 return phy_readby_cr10(iobase, phy_addr, offset); 869 /* M5261/M5263 Chip */ 870 ioaddr = iobase + DCR9; 871 872 /* Send 33 synchronization clock to Phy controller */ 873 for (i = 0; i < 35; i++) 874 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 875 876 /* Send start command(01) to Phy */ 877 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); 878 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 879 880 /* Send read command(10) to Phy */ 881 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 882 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); 883 884 /* Send Phy address */ 885 for (i = 0x10; i > 0; i = i >> 1) 886 phy_write_1bit(ioaddr, phy_addr & i ? 887 PHY_DATA_1 : PHY_DATA_0, chip_id); 888 889 /* Send register address */ 890 for (i = 0x10; i > 0; i = i >> 1) 891 phy_write_1bit(ioaddr, offset & i ? 892 PHY_DATA_1 : PHY_DATA_0, chip_id); 893 894 /* Skip transition state */ 895 phy_read_1bit(ioaddr, chip_id); 896 897 /* read 16bit data */ 898 for (phy_data = 0, i = 0; i < 16; i++) { 899 phy_data <<= 1; 900 phy_data |= phy_read_1bit(ioaddr, chip_id); 901 } 902 903 return phy_data; 904 } 905 906 static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset) 907 { 908 unsigned long ioaddr, cr10_value; 909 910 ioaddr = iobase + DCR10; 911 cr10_value = phy_addr; 912 cr10_value = (cr10_value<<5) + offset; 913 cr10_value = (cr10_value<<16) + 0x08000000; 914 outl(cr10_value, ioaddr); 915 udelay(1); 916 while (1) { 917 cr10_value = inl(ioaddr); 918 if (cr10_value & 0x10000000) 919 break; 920 } 921 return (cr10_value&0x0ffff); 922 } 923 924 static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, 925 u8 offset, u16 phy_data) 926 { 927 unsigned long ioaddr, cr10_value; 928 929 ioaddr = iobase + DCR10; 930 cr10_value = phy_addr; 931 cr10_value = (cr10_value<<5) + offset; 932 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data; 933 outl(cr10_value, ioaddr); 934 udelay(1); 935 } 936 /* 937 * Write one bit data to Phy Controller 938 */ 939 940 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id) 941 { 942 outl(phy_data , ioaddr); /* MII Clock Low */ 943 udelay(1); 944 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ 945 udelay(1); 946 outl(phy_data , ioaddr); /* MII Clock Low */ 947 udelay(1); 948 } 949 950 /* 951 * Read one bit phy data from PHY controller 952 */ 953 954 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id) 955 { 956 u16 phy_data; 957 958 outl(0x50000 , ioaddr); 959 udelay(1); 960 phy_data = (inl(ioaddr) >> 19) & 0x1; 961 outl(0x40000 , ioaddr); 962 udelay(1); 963 964 return phy_data; 965 } 966 967 /* 968 * Set MAC address to ID Table 969 */ 970 971 static void set_mac_addr(struct eth_device *dev) 972 { 973 int i; 974 u16 addr; 975 struct uli526x_board_info *db = dev->priv; 976 outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */ 977 /* Reset dianostic pointer port */ 978 outl(0x1c0, db->ioaddr + DCR13); 979 outl(0, db->ioaddr + DCR14); /* Clear reset port */ 980 outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */ 981 outl(0, db->ioaddr + DCR14); /* Clear reset port */ 982 outl(0, db->ioaddr + DCR13); /* Clear CR13 */ 983 /* Select ID Table access port */ 984 outl(0x1b0, db->ioaddr + DCR13); 985 /* Read MAC address from CR14 */ 986 for (i = 0; i < 3; i++) { 987 addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8); 988 outl(addr, db->ioaddr + DCR14); 989 } 990 /* write end */ 991 outl(0, db->ioaddr + DCR13); /* Clear CR13 */ 992 outl(0, db->ioaddr + DCR0); /* Clear CR0 */ 993 udelay(10); 994 return; 995 } 996
