| /external/llvm/test/MC/AArch64/ |
| armv8.2a-persistent-memory.s | 4 dc cvap, x7
5 // CHECK: dc cvap, x7 // encoding: [0x27,0x7c,0x0b,0xd5]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| armv8.2a-persistent-memory.s | 4 dc cvap, x7
5 // CHECK: dc cvap, x7 // encoding: [0x27,0x7c,0x0b,0xd5]
|
| /external/libavc/common/ |
| ih264_common_tables.c | 443 { 0x0, 0x1, 0xc, 0x7, 0x1, 0x1, 0xf, 0x7, 0xc, 0xf, 0xc, 0x7, 0xf, 0x7, 0xf, 0x7 },
444 { 0x1, 0x1, 0xf, 0x7, 0x1, 0x1, 0xf, 0x7, 0xf, 0xf, 0xf, 0x7, 0xf, 0x7, 0xf, 0x7 },
[all...] |
| /external/libgsm/src/ |
| gsm_decode.c | 37 LARc[6] = sr & 0x7; sr >>= 3;
38 LARc[7] = sr & 0x7; sr >>= 3;
45 xmc[0] = sr & 0x7; sr >>= 3;
47 xmc[1] = sr & 0x7; sr >>= 3;
48 xmc[2] = sr & 0x7; sr >>= 3;
50 xmc[3] = sr & 0x7; sr >>= 3;
51 xmc[4] = sr & 0x7; sr >>= 3;
52 xmc[5] = sr & 0x7; sr >>= 3;
54 xmc[6] = sr & 0x7; sr >>= 3;
55 xmc[7] = sr & 0x7; sr >>= 3
[all...] |
| gsm_explode.c | 40 LARc[6] = sr & 0x7; sr >>= 3;
41 LARc[7] = sr & 0x7; sr >>= 3;
50 xmc[0] = sr & 0x7; sr >>= 3;
52 xmc[1] = sr & 0x7; sr >>= 3;
53 xmc[2] = sr & 0x7; sr >>= 3;
55 xmc[3] = sr & 0x7; sr >>= 3;
56 xmc[4] = sr & 0x7; sr >>= 3;
57 xmc[5] = sr & 0x7; sr >>= 3;
59 xmc[6] = sr & 0x7; sr >>= 3;
60 xmc[7] = sr & 0x7; sr >>= 3
[all...] |
| gsm_print.c | 28 LARc[3] = (*c++ & 0x7) << 2;
33 LARc[6] = (*c >> 3) & 0x7;
34 LARc[7] = *c++ & 0x7;
43 xmc[0] = (*c >> 4) & 0x7;
44 xmc[1] = (*c >> 1) & 0x7;
47 xmc[3] = (*c >> 3) & 0x7;
48 xmc[4] = *c++ & 0x7;
49 xmc[5] = (*c >> 5) & 0x7;
50 xmc[6] = (*c >> 2) & 0x7;
53 xmc[8] = (*c >> 4) & 0x7;
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/include/plat/arm/common/aarch64/ |
| cci_macros.S | 25 /* Store in x7 the base address of the first interface */
26 mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
28 ldr w8, [x7, #SNOOP_CTRL_REG]
29 /* Store in x7 the base address of the second interface */
30 mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
32 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| arm_macros.S | 42 mrs x7, id_aa64pfr0_el1
43 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
44 cmp x7, #1
74 add x7, x16, #GICD_ISPENDR
78 sub x4, x7, x16
86 ldr x4, [x7], #8
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/ |
| PL35xSmc.h | 31 #define PL350_SMC_DIRECT_CMD_ADDR_CS(ChipSelect) (((ChipSelect) & 0x7) << 23)
61 #define PL350_SMC_SET_CYCLE_NAND_T_REA(t) (((t) & 0x7) << 8)
62 #define PL350_SMC_SET_CYCLE_NAND_T_WP(t) (((t) & 0x7) << 11)
63 #define PL350_SMC_SET_CYCLE_NAND_T_CLR(t) (((t) & 0x7) << 14)
64 #define PL350_SMC_SET_CYCLE_NAND_T_AR(t) (((t) & 0x7) << 17)
65 #define PL350_SMC_SET_CYCLE_NAND_T_RR(t) (((t) & 0x7) << 20)
69 #define PL350_SMC_SET_CYCLE_SRAM_T_CEOE(t) (((t) & 0x7) << 8)
70 #define PL350_SMC_SET_CYCLE_SRAM_T_WP(t) (((t) & 0x7) << 11)
71 #define PL350_SMC_SET_CYCLE_SRAM_T_PC(t) (((t) & 0x7) << 14)
72 #define PL350_SMC_SET_CYCLE_SRAM_T_TR(t) (((t) & 0x7) << 17)
[all...] |
| /external/u-boot/arch/nds32/include/asm/ |
| cache.h | 37 #define ICM_CFG_MSK_ISET (0x7 << ICM_CFG_OFF_ISET)
38 #define ICM_CFG_MSK_IWAY (0x7 << ICM_CFG_OFF_IWAY)
43 #define DCM_CFG_MSK_DSET (0x7 << DCM_CFG_OFF_DSET)
44 #define DCM_CFG_MSK_DWAY (0x7 << DCM_CFG_OFF_DWAY)
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/common/include/ |
| plat_macros.S | 51 mrs x7, id_aa64pfr0_el1
52 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
53 cmp x7, #1
83 add x7, x16, #GICD_ISPENDR
87 sub x4, x7, x16
95 ldr x4, [x7], #8
105 /* Store in x7 the base address of the first interface */
106 mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \
108 ldr w8, [x7, #SNOOP_CTRL_REG
[all...] |
| /external/clang/test/Frontend/ |
| backend-diagnostic.c | 28 int x5, int x6, int x7, int x8, int x9) {
30 "r" (x4),"r" (x5),"r" (x6),"r" (x7),"r" (x8),"r" (x9));
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/include/ |
| plat_macros.S | 50 add x7, x16, #GICD_ISPENDR
54 sub x4, x7, x16
60 ldr x4, [x7], #8
67 /* Store in x7 the base address of the first interface */
68 mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \
70 ldr w8, [x7, #SNOOP_CTRL_REG]
71 /* Store in x7 the base address of the second interface */
72 mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \
74 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/include/ |
| plat_macros.S | 50 add x7, x16, #GICD_ISPENDR
54 sub x4, x7, x16
60 ldr x4, [x7], #8
67 /* Store in x7 the base address of the first interface */
68 mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
70 ldr w8, [x7, #SNOOP_CTRL_REG]
71 /* Store in x7 the base address of the second interface */
72 mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
74 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt6795/include/ |
| plat_macros.S | 42 add x7, x16, #GICD_ISPENDR
46 sub x4, x7, x16
54 ldr x4, [x7], #8
76 /* Store in x7 the base address of the first interface */
77 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
79 ldr w8, [x7, #SNOOP_CTRL_REG]
80 /* Store in x7 the base address of the second interface */
81 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
83 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/include/ |
| plat_macros.S | 47 add x7, x16, #GICD_ISPENDR
51 sub x4, x7, x16
59 ldr x4, [x7], #8
68 /* Store in x7 the base address of the first interface */
69 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
71 ldr w8, [x7, #SNOOP_CTRL_REG]
72 /* Store in x7 the base address of the second interface */
73 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
75 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| /external/clang/test/SemaCXX/ |
| attr-selectany.cpp | 20 // FIXME: MSVC accepts this and makes x7 externally visible and comdat, but keep
22 static int x7; // expected-note{{previous definition}} variable
23 extern __declspec(selectany) int x7; // expected-warning{{attribute declaration must precede definition}} variable
25 int asdf() { return x7; }
|
| /external/llvm/test/MC/AMDGPU/ |
| mimg.s | 5 image_load v[4:6], v[237:240], s[28:35] dmask:0x7 unorm
6 // SICI: image_load v[4:6], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x00,0xf0,0xed,0x04,0x07,0x00]
7 // VI: image_load v[4:6], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x00,0xf0,0xed,0x04,0x07,0x00]
9 image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm
10 // SICI: image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x20,0xf0,0xed,0xc1,0x07,0x00]
11 // VI : image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x20,0xf0,0xed,0xc1,0x07,0x00]
13 image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 unorm
14 // SICI: image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 unorm ; encoding: [0x00,0x17,0x80,0xf0,0xed,0xc1,0x27,0x00]
15 // VI : image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 unorm ; encoding: [0x00,0x17,0x80,0xf0,0xed,0xc1,0x27,0x00]
|
| /external/u-boot/include/synopsys/ |
| dwcddr21mctl.h | 67 #define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3)
68 #define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6)
83 #define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26)
110 #define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2)
111 #define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5)
142 #define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2)
144 #define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6)
154 #define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0)
155 #define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3)
156 #define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6
[all...] |
| /external/u-boot/board/samsung/odroid/ |
| setup.h | 11 #define SDIV(x) ((x) & 0x7)
27 #define APLL_SEL(x) ((x) & 0x7)
28 #define CORE_SEL(x) (((x) & 0x7) << 16)
29 #define HPM_SEL(x) (((x) & 0x7) << 20)
30 #define MPLL_USER_SEL_C(x) (((x) & 0x7) << 24)
37 #define CORE_RATIO(x) ((x) & 0x7)
38 #define COREM0_RATIO(x) (((x) & 0x7) << 4)
39 #define COREM1_RATIO(x) (((x) & 0x7) << 8)
40 #define PERIPH_RATIO(x) (((x) & 0x7) << 12)
41 #define ATB_RATIO(x) (((x) & 0x7) << 16
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/include/lib/cpus/aarch32/ |
| cortex_a53.h | 20 #define RETENTION_ENTRY_TICKS_512 0x7
30 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
33 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
63 #define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
|
| /external/u-boot/board/freescale/ls2080ardb/ |
| ls2080ardb_qixis.h | 17 #define QIXIS_SYSCLK_166 0x7
|
| /frameworks/av/media/libstagefright/codecs/amrnb/dec/src/ |
| d4_17pf.cpp | 199 i = index & 0x7;
208 i = index & 0x7;
218 i = index & 0x7;
234 i = index & 0x7;
|
| /external/strace/tests/ |
| init_delete_module.h | 59 printf("\\%u%u%u", (i >> 6) & 0x3, (i >> 3) & 0x7, i & 0x7);
|
| /external/strace/tests-m32/ |
| init_delete_module.h | 59 printf("\\%u%u%u", (i >> 6) & 0x3, (i >> 3) & 0x7, i & 0x7);
|
