1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __ROCKCHIP_PLAT_MACROS_S__ 7 #define __ROCKCHIP_PLAT_MACROS_S__ 8 9 #include <cci.h> 10 #include <gic_common.h> 11 #include <gicv2.h> 12 #include <gicv3.h> 13 #include <platform_def.h> 14 15 .section .rodata.gic_reg_name, "aS" 16 /* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 17 gicc_regs: 18 .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 19 20 /* Applicable only to GICv3 with SRE enabled */ 21 icc_regs: 22 .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 23 24 /* Registers common to both GICv2 and GICv3 */ 25 gicd_pend_reg: 26 .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ 27 " Offset:\t\t\tvalue\n" 28 newline: 29 .asciz "\n" 30 spacer: 31 .asciz ":\t\t0x" 32 33 .section .rodata.cci_reg_name, "aS" 34 cci_iface_regs: 35 .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" 36 37 /* --------------------------------------------- 38 * The below utility macro prints out relevant GIC 39 * and CCI registers whenever an unhandled 40 * exception is taken in BL31. 41 * Expects: GICD base in x16, GICC base in x17 42 * Clobbers: x0 - x10, sp 43 * --------------------------------------------- 44 */ 45 .macro plat_crash_print_regs 46 47 mov_imm x16, PLAT_RK_GICD_BASE 48 mov_imm x17, PLAT_RK_GICC_BASE 49 50 /* Check for GICv3 system register access */ 51 mrs x7, id_aa64pfr0_el1 52 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 53 cmp x7, #1 54 b.ne print_gicv2 55 56 /* Check for SRE enable */ 57 mrs x8, ICC_SRE_EL3 58 tst x8, #ICC_SRE_SRE_BIT 59 b.eq print_gicv2 60 61 /* Load the icc reg list to x6 */ 62 adr x6, icc_regs 63 /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 64 mrs x8, ICC_HPPIR0_EL1 65 mrs x9, ICC_HPPIR1_EL1 66 mrs x10, ICC_CTLR_EL3 67 /* Store to the crash buf and print to console */ 68 bl str_in_crash_buf_print 69 b print_gic_common 70 71 print_gicv2: 72 /* Load the gicc reg list to x6 */ 73 adr x6, gicc_regs 74 /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 75 ldr w8, [x17, #GICC_HPPIR] 76 ldr w9, [x17, #GICC_AHPPIR] 77 ldr w10, [x17, #GICC_CTLR] 78 /* Store to the crash buf and print to console */ 79 bl str_in_crash_buf_print 80 81 print_gic_common: 82 /* Print the GICD_ISPENDR regs */ 83 add x7, x16, #GICD_ISPENDR 84 adr x4, gicd_pend_reg 85 bl asm_print_str 86 gicd_ispendr_loop: 87 sub x4, x7, x16 88 cmp x4, #0x280 89 b.eq exit_print_gic_regs 90 bl asm_print_hex 91 92 adr x4, spacer 93 bl asm_print_str 94 95 ldr x4, [x7], #8 96 bl asm_print_hex 97 98 adr x4, newline 99 bl asm_print_str 100 b gicd_ispendr_loop 101 exit_print_gic_regs: 102 103 #if PLATFORM_CLUSTER_COUNT > 1 104 adr x6, cci_iface_regs 105 /* Store in x7 the base address of the first interface */ 106 mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \ 107 PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX)) 108 ldr w8, [x7, #SNOOP_CTRL_REG] 109 /* Store in x7 the base address of the second interface */ 110 mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \ 111 PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX)) 112 ldr w9, [x7, #SNOOP_CTRL_REG] 113 /* Store to the crash buf and print to console */ 114 bl str_in_crash_buf_print 115 #endif 116 .endm 117 118 #endif /* __ROCKCHIP_PLAT_MACROS_S__ */ 119
