| /external/clang/lib/StaticAnalyzer/Core/ |
| ExprEngineC.cpp | [all...] |
| BugReporterVisitors.cpp | 715 ID.Add(Constraint);
726 return N->getState()->isNull(Constraint).isUnderconstrained();
727 return (bool)N->getState()->assume(Constraint, !Assumption);
746 // Check if in the previous state it was feasible for this constraint
752 // As a sanity check, make sure that the negation of the constraint
757 // We found the transition point for the constraint. We now need to
758 // pretty-print the constraint. (work-in-progress)
762 if (Constraint.getAs<Loc>()) {
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 360 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
361 // First, see if this is a constraint that directly corresponds to a
363 if (Constraint.size() == 1) {
364 switch (Constraint[0]) {
383 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 745 SystemZTargetLowering::getConstraintType(StringRef Constraint) const {
746 if (Constraint.size() == 1) {
747 switch (Constraint[0]) {
774 return TargetLowering::getConstraintType(Constraint);
779 const char *constraint) const {
787 // Look at the constraint type.
788 switch (*constraint) {
790 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
845 // Parse a "{tNNN}" register constraint for which the register type "t"
849 parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC
[all...] |
| /external/clang/lib/Parse/ |
| ParseStmtAsm.cpp | 626 // Recast the void pointers and build the vector of constraint StringRefs.
838 ExprResult Constraint(ParseAsmStringLiteral());
839 if (Constraint.isInvalid()) {
843 Constraints.push_back(Constraint.get());
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 600 ConstraintType getConstraintType(StringRef Constraint) const override;
602 /// Examine constraint string and operand type and determine a weight value.
605 AsmOperandInfo &info, const char *constraint) const override;
609 StringRef Constraint, MVT VT) const override;
620 std::string &Constraint,
680 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 691 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
793 ConstraintType getConstraintType(StringRef Constraint) const override;
795 /// Examine constraint string and operand type and determine a weight value.
799 const char *constraint) const override;
805 /// constraint of the inline asm instruction being processed is 'm'.
807 std::string &Constraint,
824 /// Given a physical register constraint
830 StringRef Constraint, MVT VT) const override;
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| TargetLowering.h | 646 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| X86RecognizableInstr.cpp | 573 const CGIOperandList::ConstraintInfo &Constraint =
575 if (Constraint.isTied()) {
576 operandMapping[operandIndex] = Constraint.getTiedOperand();
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 655 ConstraintType getConstraintType(StringRef Constraint) const override;
659 /// Examine constraint string and operand type and determine a weight value.
663 const char *constraint) const override;
667 StringRef Constraint, MVT VT) const override;
671 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 395 ConstraintType getConstraintType(StringRef Constraint) const override;
397 /// Examine constraint string and operand type and determine a weight value.
400 AsmOperandInfo &info, const char *constraint) const override;
404 StringRef Constraint, MVT VT) const override;
410 /// true it means one of the asm constraint of the inline asm instruction
412 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 712 ConstraintType getConstraintType(StringRef Constraint) const override;
714 /// Examine constraint string and operand type and determine a weight value.
717 AsmOperandInfo &info, const char *constraint) const override;
721 StringRef Constraint, MVT VT) const override;
732 std::string &Constraint,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| CodeGenInstruction.cpp | 130 // constraint info, even if none is present.
214 PrintFatalError("Illegal format for @earlyclobber constraint: '" + CStr + "'");
226 // Only other constraint is "TIED_TO" for now.
228 assert(pos != std::string::npos && "Unrecognized constraint");
235 PrintFatalError("Illegal format for tied-to constraint: '" + CStr + "'");
242 PrintFatalError("Illegal format for tied-to constraint: '" + CStr + "'");
443 if (DefInit *Constraint = dyn_cast<DefInit>(ConstraintList->getArg(i))) {
444 return Constraint->getDef()->isSubClassOf("TypedOperand") &&
445 Constraint->getDef()->getValueAsBit("IsPointer");
|
| X86RecognizableInstr.cpp | 423 const CGIOperandList::ConstraintInfo &Constraint =
425 if (Constraint.isTied()) {
427 operandMapping[Constraint.getTiedOperand()] = operandIndex;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 555 SystemZTargetLowering::getConstraintType(StringRef Constraint) const {
556 if (Constraint.size() == 1) {
557 switch (Constraint[0]) {
583 return TargetLowering::getConstraintType(Constraint);
588 const char *constraint) const {
596 // Look at the constraint type.
597 switch (*constraint) {
599 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
648 // Parse a "{tNNN}" register constraint for which the register type "t"
652 parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC
[all...] |
| /external/llvm/utils/TableGen/ |
| AsmMatcherEmitter.cpp | 545 void formTwoOperandAlias(StringRef Constraint);
800 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
818 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
821 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
[all...] |
| X86RecognizableInstr.cpp | 528 const CGIOperandList::ConstraintInfo &Constraint =
530 if (Constraint.isTied()) {
532 operandMapping[Constraint.getTiedOperand()] = operandIndex;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 702 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
878 ConstraintType getConstraintType(StringRef Constraint) const override;
880 /// Examine constraint string and operand type and determine a weight value.
884 const char *constraint) const override;
890 /// constraint of the inline asm instruction being processed is 'm'.
892 std::string &Constraint,
909 /// Given a physical register constraint
915 StringRef Constraint, MVT VT) const override;
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
