| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 253 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
258 bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
270 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
299 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
544 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
546 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
589 SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
590 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
591 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
592 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| ObjCARCAnalysisUtils.h | 140 inline bool IsPotentialRetainableObjPtr(const Value *Op) {
143 if (isa<Constant>(Op) || isa<AllocaInst>(Op))
146 if (const Argument *Arg = dyn_cast<Argument>(Op))
157 PointerType *Ty = dyn_cast<PointerType>(Op->getType());
165 inline bool IsPotentialRetainableObjPtr(const Value *Op,
168 if (!IsPotentialRetainableObjPtr(Op))
172 if (AA.pointsToConstantMemory(Op))
176 if (const LoadInst *LI = dyn_cast<LoadInst>(Op))
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIInsertWaits.cpp | 103 bool isOpRelevant(MachineOperand &Op);
225 bool SIInsertWaits::isOpRelevant(MachineOperand &Op) {
227 if (!Op.isReg() || !TRI->isInAllocatableClass(Op.getReg()))
231 if (Op.isDef())
235 MachineInstr &MI = *Op.getParent();
250 if (Data && Op.isIdenticalTo(*Data))
256 if (Data0 && Op.isIdenticalTo(*Data0))
260 return Data1 && Op.isIdenticalTo(*Data1);
269 return Op.isIdenticalTo(*I)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.h | 56 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
107 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
108 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
109 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
110 SDValue lowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
111 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
112 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 61 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
68 void computeKnownBitsForTargetNode(const SDValue Op,
84 void LowerAsmOperandForConstraint(SDValue Op,
169 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
171 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
172 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
174 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG,
176 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG,
180 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 91 MachineOperand &Op = MI->getOperand(Operand);
92 if (Op.isReg()) {
94 AM.Base.Reg = Op.getReg();
97 AM.Base.FrameIndex = Op.getIndex();
99 Op = MI->getOperand(Operand + 1);
100 if (Op.isImm())
101 AM.Scale = Op.getImm();
102 Op = MI->getOperand(Operand + 2);
103 if (Op.isImm())
104 AM.IndexReg = Op.getImm()
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenInstruction.h | 45 static ConstraintInfo getTied(unsigned Op) {
48 I.OtherTiedOperand = Op;
173 std::pair<unsigned,unsigned> ParseOperandName(const std::string &Op,
178 unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const {
179 return OperandList[Op.first].MIOperandNo + Op.second;
184 std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const {
187 if (OperandList[i].MIOperandNo+OperandList[i].MINumOperands > Op)
188 return std::make_pair(i, Op-OperandList[i].MIOperandNo);
196 std::pair<unsigned,unsigned> Op = getSubOperandNumber(FlatOpNo)
[all...] |
| /external/skia/src/core/ |
| SkRasterClip.h | 21 inline void applyClipRestriction(SkRegion::Op op, SkIRect* bounds) {
22 if (op >= SkRegion::kUnion_Op && fClipRestrictionRect
43 void opRect(const SkRect&, const SkMatrix&, const SkIRect& limit, SkRegion::Op, bool isAA);
44 void opRRect(const SkRRect&, const SkMatrix&, const SkIRect& limit, SkRegion::Op, bool isAA);
45 void opPath(const SkPath&, const SkMatrix&, const SkIRect& limit, SkRegion::Op, bool isAA);
46 void opRegion(const SkRegion&, SkRegion::Op);
47 void opIRect(const SkIRect&, SkRegion::Op);
95 bool op(const SkIRect&, SkRegion::Op);
[all...] |
| /external/skqp/src/core/ |
| SkRasterClip.h | 21 inline void applyClipRestriction(SkRegion::Op op, SkIRect* bounds) {
22 if (op >= SkRegion::kUnion_Op && fClipRestrictionRect
43 void opRect(const SkRect&, const SkMatrix&, const SkIRect& limit, SkRegion::Op, bool isAA);
44 void opRRect(const SkRRect&, const SkMatrix&, const SkIRect& limit, SkRegion::Op, bool isAA);
45 void opPath(const SkPath&, const SkMatrix&, const SkIRect& limit, SkRegion::Op, bool isAA);
46 void opRegion(const SkRegion&, SkRegion::Op);
47 void opIRect(const SkIRect&, SkRegion::Op);
95 bool op(const SkIRect&, SkRegion::Op);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 72 SDValue Op(Node, ResNo);
74 VRBaseMap.erase(Op);
75 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
107 SDValue Op = User->getOperand(i);
108 if (Op.getNode() != Node || Op.getResNo() != ResNo)
110 EVT VT = Node->getValueType(Op.getResNo());
161 SDValue Op(Node, ResNo);
163 VRBaseMap.erase(Op);
164 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| CodeGenInstruction.h | 45 static ConstraintInfo getTied(unsigned Op) {
48 I.OtherTiedOperand = Op;
168 std::pair<unsigned,unsigned> ParseOperandName(const std::string &Op,
173 unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const {
174 return OperandList[Op.first].MIOperandNo + Op.second;
179 std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const {
182 if (OperandList[i].MIOperandNo+OperandList[i].MINumOperands > Op)
183 return std::make_pair(i, Op-OperandList[i].MIOperandNo);
191 std::pair<unsigned,unsigned> Op = getSubOperandNumber(FlatOpNo)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIOptimizeExecMaskingPreRA.cpp | 85 auto Op = TII.getNamedOperand(MI, AMDGPU::OpName::src1);
86 if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
87 return Op->getReg();
88 Op = TII.getNamedOperand(MI, AMDGPU::OpName::src0);
89 if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
90 return Op->getReg();
150 for (auto &Op : I->operands()) {
151 if (Op.isReg()
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 80 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
86 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 61 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
68 void computeKnownBitsForTargetNode(const SDValue Op,
84 void LowerAsmOperandForConstraint(SDValue Op,
169 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
171 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
172 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
174 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG,
176 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG,
180 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| CodeGenInstruction.h | 45 static ConstraintInfo getTied(unsigned Op) {
48 I.OtherTiedOperand = Op;
173 std::pair<unsigned,unsigned> ParseOperandName(const std::string &Op,
178 unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const {
179 return OperandList[Op.first].MIOperandNo + Op.second;
184 std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const {
187 if (OperandList[i].MIOperandNo+OperandList[i].MINumOperands > Op)
188 return std::make_pair(i, Op-OperandList[i].MIOperandNo);
196 std::pair<unsigned,unsigned> Op = getSubOperandNumber(FlatOpNo)
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.cpp | 154 void AddBusyRegs(const X86Operand &Op) {
155 AddBusyReg(Op.getMemBaseReg());
156 AddBusyReg(Op.getMemIndexReg());
210 virtual void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
214 virtual void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
222 void InstrumentMemOperand(X86Operand &Op, unsigned AccessSize, bool IsWrite,
236 void EmitLEA(X86Operand &Op, unsigned Size, unsigned Reg, MCStreamer &Out) {
241 Op.addMemOperands(Inst, 5);
245 void ComputeMemOperandAddress(X86Operand &Op, unsigned Size,
251 std::unique_ptr<X86Operand> AddDisplacement(X86Operand &Op,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.cpp | 166 void AddBusyRegs(const X86Operand &Op) {
167 AddBusyReg(Op.getMemBaseReg());
168 AddBusyReg(Op.getMemIndexReg());
221 virtual void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
225 virtual void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
233 void InstrumentMemOperand(X86Operand &Op, unsigned AccessSize, bool IsWrite,
247 void EmitLEA(X86Operand &Op, unsigned Size, unsigned Reg, MCStreamer &Out) {
252 Op.addMemOperands(Inst, 5);
256 void ComputeMemOperandAddress(X86Operand &Op, unsigned Size,
262 std::unique_ptr<X86Operand> AddDisplacement(X86Operand &Op,
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 81 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW,
83 setOperationAction(Op, T, Expand);
86 for (auto Op :
88 setOperationAction(Op, T, Legal);
96 for (auto Op :
101 setOperationAction(Op, T, Expand);
120 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
121 setOperationAction(Op, T, Expand);
526 SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
528 SDLoc DL(Op);
[all...] |
| /external/llvm/utils/PerfectShuffle/ |
| PerfectShuffle.cpp | 88 Operator *Op; // The Operation used to generate this value.
147 static const char *getZeroCostOpName(unsigned short Op) {
148 if (ShufTab[Op].Arg0 == 0x0123)
150 else if (ShufTab[Op].Arg0 == 0x4567)
162 std::cerr << " = " << ShufTab[ThisOp].Op->getName() << "(";
176 if (!ShufTab[Vals[ValNo]].Op->isOnlyLHSOperator()) {
222 ShufTab[0x0123].Op = nullptr;
225 ShufTab[0x4567].Op = nullptr;
304 Operator *Op = TheOperators[opnum];
306 // Evaluate op(LHS,LHS
[all...] |
| /external/swiftshader/third_party/LLVM/utils/PerfectShuffle/ |
| PerfectShuffle.cpp | 89 Operator *Op; // The Operation used to generate this value.
147 static const char *getZeroCostOpName(unsigned short Op) {
148 if (ShufTab[Op].Arg0 == 0x0123)
150 else if (ShufTab[Op].Arg0 == 0x4567)
162 std::cerr << " = " << ShufTab[ThisOp].Op->getName() << "(";
176 if (!ShufTab[Vals[ValNo]].Op->isOnlyLHSOperator()) {
222 ShufTab[0x0123].Op = 0;
225 ShufTab[0x4567].Op = 0;
304 Operator *Op = TheOperators[opnum];
306 // Evaluate op(LHS,LHS
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/PerfectShuffle/ |
| PerfectShuffle.cpp | 88 Operator *Op; // The Operation used to generate this value.
147 static const char *getZeroCostOpName(unsigned short Op) {
148 if (ShufTab[Op].Arg0 == 0x0123)
150 else if (ShufTab[Op].Arg0 == 0x4567)
162 std::cerr << " = " << ShufTab[ThisOp].Op->getName() << "(";
176 if (!ShufTab[Vals[ValNo]].Op->isOnlyLHSOperator()) {
222 ShufTab[0x0123].Op = nullptr;
225 ShufTab[0x4567].Op = nullptr;
304 Operator *Op = TheOperators[opnum];
306 // Evaluate op(LHS,LHS
[all...] |
| /external/eigen/unsupported/Eigen/CXX11/src/Tensor/ |
| TensorReductionCuda.h | 263 template <typename Op>
264 __global__ void ReductionCleanupKernelHalfFloat(Op& reducer, half* output, half2* scratch) {
273 template <typename Self, typename Op, typename OutputType, bool PacketAccess, typename Enabled = void>
275 static void run(const Self&, Op&, const GpuDevice&, OutputType*, typename Self::Index) {
281 template <typename Self, typename Op, typename OutputType, bool PacketAccess>
283 Self, Op, OutputType, PacketAccess,
288 static void run(const Self& self, Op& reducer, const GpuDevice& device, OutputType* output, typename Self::Index num_coeffs) {
300 LAUNCH_CUDA_KERNEL((FullReductionKernel<block_size, num_per_thread, Self, Op, Index>),
306 template <typename Self, typename Op>
307 struct FullReductionLauncher<Self, Op, Eigen::half, false>
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 306 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
327 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
654 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
673 void computeKnownBitsForTargetNode(const SDValue Op,
731 void LowerAsmOperandForConstraint(SDValue Op,
[all...] |
| /external/tensorflow/tensorflow/compiler/xla/service/ |
| pattern_matcher_test.cc | 45 match::Op(&matched_inst)
53 match::Op(&matched_operand).WithOpcode(HloOpcode::kConstant))));
62 match::Op().WithName("bad_name")));
65 match::Multiply(&matched_inst, match::Op(), match::Op())));
193 root, match::Op().WithFusionKind(HloInstruction::FusionKind::kLoop)));
195 root, match::Op().WithFusionKind(HloInstruction::FusionKind::kInput)));
196 EXPECT_FALSE(Match(root->operand(0), match::Op().WithFusionKind(
211 EXPECT_FALSE(Match(root, match::Op().WithTupleIndex(0)));
212 EXPECT_TRUE(Match(root, match::Op().WithTupleIndex(1)))
[all...] |
| /external/llvm/lib/Target/Lanai/AsmParser/ |
| LanaiAsmParser.cpp | 568 auto Op = make_unique<LanaiOperand>(TOKEN);
569 Op->Tok.Data = Str.data();
570 Op->Tok.Length = Str.size();
571 Op->StartLoc = Start;
572 Op->EndLoc = Start;
573 return Op;
578 auto Op = make_unique<LanaiOperand>(REGISTER);
579 Op->Reg.RegNum = RegNum;
580 Op->StartLoc = Start;
581 Op->EndLoc = End
[all...] |
