| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.cpp | 476 SDValue Op = OrigOp;
478 AnalyzeNewValue(Op); // Op may morph.
480 if (Op.getNode()->getNodeId() == Processed)
485 NewOps.push_back(Op);
486 } else if (Op != OrigOp) {
489 NewOps.push_back(Op);
732 void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
734 TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
738 SDValue &OpEntry = PromotedIntegers[Op];
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 78 static MachineOperand earlyUseOperand(MachineOperand Op) {
79 if (Op.isReg())
80 Op.setIsKill(false);
81 return Op;
432 // structure, but VAEND is a no-op.
728 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
735 if (auto *C = dyn_cast<ConstantSDNode>(Op))
737 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
738 Op.getValueType()));
742 if (auto *C = dyn_cast<ConstantSDNode>(Op))
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 60 << *Ops[0].Op->getType() << '\t';
63 Ops[i].Op->printAsOperand(dbgs(), false, M);
259 Neg->setOperand(1, Constant::getNullValue(Ty)); // Drop use of op.
279 /// The existing weight LHS represents the computation X op X op ... op X where
280 /// X occurs LHS times. The combined weight represents X op X op ... op X with
281 /// X occurring LHS + RHS times. If op is "Xor" for example then the combine
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 259 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
280 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
546 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
565 void computeKnownBitsForTargetNode(const SDValue Op,
619 void LowerAsmOperandForConstraint(SDValue Op,
760 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/AsmPrinter/ |
| DebugHandlerBase.cpp | 44 auto Op = DIExpr->expr_op_begin();
45 while (Op != DIExpr->expr_op_end()) {
46 switch (Op->getOp()) {
48 int Value = Op->getArg(0);
49 ++Op;
50 if (Op != DIExpr->expr_op_end()) {
51 switch (Op->getOp()) {
64 Offset += Op->getArg(0);
67 Location.FragmentInfo = {Op->getArg(1), Op->getArg(0)}
[all...] |
| /external/tensorflow/tensorflow/core/framework/ |
| node_def_builder_test.cc | 35 void Op(const OpDefBuilder& op_def_builder) {
41 // Resets builder_ with a new NodeDefBuilder using the Op from the last call
42 // to Op() above.
44 EXPECT_FALSE(op_def_.name().empty()) << "Must call Op() before Builder()";
117 Op(OpDefBuilder("Simple").Input("a: int32").Output("out: float"));
120 R"proto( op: "Simple" input: "x" )proto");
124 R"proto( op: "Simple" input: "y:2" )proto");
128 op: "Simple" input: "a" )proto");
131 R"proto( op: "Simple" input: "a" )proto");
135 {DT_FLOAT}, R"proto( op: "Simple" input: "a" )proto")
[all...] |
| /external/llvm/lib/IR/ |
| ConstantsContext.h | 42 : ConstantExpr(Ty, Opcode, &Op<0>(), 1) {
43 Op<0>() = C;
60 : ConstantExpr(C1->getType(), Opcode, &Op<0>(), 2) {
61 Op<0>() = C1;
62 Op<1>() = C2;
80 : ConstantExpr(C2->getType(), Instruction::Select, &Op<0>(), 3) {
81 Op<0>() = C1;
82 Op<1>() = C2;
83 Op<2>() = C3;
102 Instruction::ExtractElement, &Op<0>(), 2)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelLowering.h | 98 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| ConstantsContext.h | 40 : ConstantExpr(Ty, Opcode, &Op<0>(), 1) {
41 Op<0>() = C;
57 : ConstantExpr(C1->getType(), Opcode, &Op<0>(), 2) {
58 Op<0>() = C1;
59 Op<1>() = C2;
76 : ConstantExpr(C2->getType(), Instruction::Select, &Op<0>(), 3) {
77 Op<0>() = C1;
78 Op<1>() = C2;
79 Op<2>() = C3;
97 Instruction::ExtractElement, &Op<0>(), 2)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/ |
| ConstantsContext.h | 49 : ConstantExpr(Ty, Opcode, &Op<0>(), 1) {
50 Op<0>() = C;
67 : ConstantExpr(C1->getType(), Opcode, &Op<0>(), 2) {
68 Op<0>() = C1;
69 Op<1>() = C2;
87 : ConstantExpr(C2->getType(), Instruction::Select, &Op<0>(), 3) {
88 Op<0>() = C1;
89 Op<1>() = C2;
90 Op<2>() = C3;
109 Instruction::ExtractElement, &Op<0>(), 2)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 156 // As we are always Sequential Consistent, an ATOMIC_FENCE becomes a no OP.
201 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
202 switch (Op.getOpcode())
204 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
205 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
206 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
207 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
208 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
209 case ISD::LOAD: return LowerLOAD(Op, DAG);
210 case ISD::STORE: return LowerSTORE(Op, DAG)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 153 // As we are always Sequential Consistent, an ATOMIC_FENCE becomes a no OP.
198 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
199 switch (Op.getOpcode())
201 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
202 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
203 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
204 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
205 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
206 case ISD::LOAD: return LowerLOAD(Op, DAG);
207 case ISD::STORE: return LowerSTORE(Op, DAG)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 179 SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
181 switch (Op.getOpcode()) {
184 case ISD::SRA: return LowerShifts(Op, DAG);
185 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
186 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
187 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
188 case ISD::SETCC: return LowerSETCC(Op, DAG);
189 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
190 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
191 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 244 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
245 switch (Op) {
257 setOperationAction(Op, VT, Custom);
260 setOperationAction(Op, VT, Expand);
478 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
479 switch (Op) {
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 164 SDValue ARCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
165 SDValue LHS = Op.getOperand(0);
166 SDValue RHS = Op.getOperand(1);
167 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
168 SDValue TVal = Op.getOperand(2);
169 SDValue FVal = Op.getOperand(3);
170 SDLoc dl(Op);
178 SDValue ARCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
180 SDValue Op0 = Op.getOperand(0);
181 SDLoc dl(Op);
[all...] |
| /external/v8/src/ |
| objects-body-descriptors-inl.h | 627 template <typename Op, typename ReturnType, typename T1, typename T2,
635 return Op::template apply<ConsString::BodyDescriptor>(p1, p2, p3, p4);
637 return Op::template apply<ThinString::BodyDescriptor>(p1, p2, p3, p4);
639 return Op::template apply<SlicedString::BodyDescriptor>(p1, p2, p3, p4);
642 return Op::template apply<ExternalOneByteString::BodyDescriptor>(
645 return Op::template apply<ExternalTwoByteString::BodyDescriptor>(
675 return Op::template apply<FixedArray::BodyDescriptor>(p1, p2, p3, p4);
677 return Op::template apply<WeakFixedArray::BodyDescriptor>(p1, p2, p3, p4);
679 return Op::template apply<WeakArrayList::BodyDescriptor>(p1, p2, p3, p4);
683 return Op::template apply<FeedbackMetadata::BodyDescriptor>(p1, p2, p3
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| MachineIRBuilder.cpp | 232 MachineInstrBuilder MachineIRBuilderBase::buildCopy(unsigned Res, unsigned Op) {
233 assert(getMRI()->getType(Res) == LLT() || getMRI()->getType(Op) == LLT() ||
234 getMRI()->getType(Res) == getMRI()->getType(Op));
235 return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
332 unsigned Op) {
333 validateTruncExt(Res, Op, true);
334 return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op);
337 MachineInstrBuilder MachineIRBuilderBase::buildSExt(unsigned Res, unsigned Op) {
338 validateTruncExt(Res, Op, true);
339 return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandCondsets.cpp | 216 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
217 Sub(Op.getSubReg()) {}
350 for (auto &Op : MI->operands()) {
351 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
353 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg());
357 Op.setIsKill(true);
411 auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> bool
[all...] |
| /external/eigen/unsupported/Eigen/CXX11/src/util/ |
| EmulateCXX11Meta.h | 257 template<typename Reducer, typename Op, typename A, std::size_t N>
261 bool result = Reducer::run(Op::run(a[0]), Op::run(a[1]));
263 result = Reducer::run(result, Op::run(a[i]));
269 template<typename Reducer, typename Op, typename A>
270 struct ArrayApplyAndReduce<Reducer, Op, A, 1> {
272 return Op::run(a[0]);
276 template<typename Reducer, typename Op, typename A, std::size_t N>
278 return ArrayApplyAndReduce<Reducer, Op, A, N>::run(a);
281 template<typename Reducer, typename Op, typename A, typename B, std::size_t N
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 125 for (SDValue Op : Ops) {
126 Entry.Node = Op;
128 Entry.isSExt = shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned);
129 Entry.isZExt = !shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned);
340 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
342 SDLoc dl(Op);
345 switch (Op.getOpcode()) {
350 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
353 if (Op.getOpcode() == ISD::XOR &&
359 EVT VT = Op.getValueType()
[all...] |
| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| NVPTXInstPrinter.cpp | 80 const MCOperand &Op = MI->getOperand(OpNo);
81 if (Op.isReg()) {
82 unsigned Reg = Op.getReg();
84 } else if (Op.isImm()) {
85 O << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
87 assert(Op.isExpr() && "Unknown operand kind in printOperand");
88 Op.getExpr()->print(O, &MAI);
281 const MCOperand &Op = MI->getOperand(OpNum);
282 assert(Op.isExpr() && "Call prototype is not an MCExpr?");
283 const MCExpr *Expr = Op.getExpr()
[all...] |
