| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 136 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/ |
| Instructions.cpp | 170 Op<-1>().set(nullptr);
189 if (NumOps < 2) NumOps = 2; // 2 op PHI nodes are VERY common.
305 Op<-1>() = Func;
331 Op<-1>() = Func;
605 Op<-3>() = Fn;
606 Op<-2>() = IfNormal;
607 Op<-1>() = IfException;
670 Op<0>() = RI.Op<0>();
679 Op<0>() = retVal
[all...] |
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| AMDGPUAsmParser.cpp | 490 auto Op = llvm::make_unique<AMDGPUOperand>(Immediate);
491 Op->Imm.Val = Val;
492 Op->Imm.IsFPImm = IsFPImm;
493 Op->Imm.Type = Type;
494 Op->Imm.Mods = {false, false, false};
495 Op->StartLoc = Loc;
496 Op->EndLoc = Loc;
497 return Op;
515 auto Op = llvm::make_unique<AMDGPUOperand>(Register);
516 Op->Reg.RegNo = RegNo
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 612 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
615 switch (Op.getOpcode()) {
616 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
617 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
618 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
619 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
621 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
622 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY);
623 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
625 case ISD::FSIN: return LowerTrig(Op, DAG)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 229 unsigned Op, raw_ostream &O,
231 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
232 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
233 const MachineOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
267 printOperand(P, MI, Op+X86::AddrBaseReg, O, Modifier);
271 printOperand(P, MI, Op+X86::AddrIndexReg, O, Modifier);
272 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
281 unsigned Op, raw_ostream &O,
283 assert(isMem(*MI, Op) && "Invalid memory reference!");
284 const MachineOperand &Segment = MI->getOperand(Op+X86::AddrSegmentReg)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 257 unsigned Op, raw_ostream &O,
259 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
260 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
261 const MachineOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
295 printOperand(P, MI, Op+X86::AddrBaseReg, O, Modifier);
299 printOperand(P, MI, Op+X86::AddrIndexReg, O, Modifier);
300 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
309 unsigned Op, raw_ostream &O,
311 assert(isMem(*MI, Op) && "Invalid memory reference!");
312 const MachineOperand &Segment = MI->getOperand(Op+X86::AddrSegmentReg)
[all...] |
| X86ISelLowering.h | 424 // 3-op Variable Permute (VPERMT2).
729 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
770 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
852 bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
857 void computeKnownBitsForTargetNode(const SDValue Op,
864 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
891 void LowerAsmOperandForConstraint(SDValue Op,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 149 const RTLIB::Libcall Op;
239 setLibcallName(LC.Op, LC.Name);
241 setCmpLibcallCC(LC.Op, LC.Cond);
246 const RTLIB::Libcall Op;
257 setLibcallName(LC.Op, LC.Name);
261 const RTLIB::Libcall Op;
272 setLibcallName(LC.Op, LC.Name);
276 const RTLIB::Libcall Op;
287 setLibcallName(LC.Op, LC.Name);
291 const RTLIB::Libcall Op;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/ObjectYAML/ |
| DWARFEmitter.cpp | 241 for (auto Op : LineTable.Opcodes) {
242 writeInteger((uint8_t)Op.Opcode, OS, DI.IsLittleEndian);
243 if (Op.Opcode == 0) {
244 encodeULEB128(Op.ExtLen, OS);
245 writeInteger((uint8_t)Op.SubOpcode, OS, DI.IsLittleEndian);
246 switch (Op.SubOpcode) {
249 writeVariableSizedInteger(Op.Data, DI.CompileUnits[0].AddrSize, OS,
253 EmitFileEntry(OS, Op.FileEntry);
258 for (auto OpByte : Op.UnknownOpcodeData)
261 } else if (Op.Opcode < LineTable.OpcodeBase)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 473 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
476 switch (Op.getOpcode()) {
477 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
478 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
479 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
480 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
482 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
483 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY);
484 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
486 case ISD::FSIN: return LowerTrig(Op, DAG)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/AsmParser/ |
| BPFAsmParser.cpp | 197 auto Op = make_unique<BPFOperand>(Token);
198 Op->Tok = Str;
199 Op->StartLoc = S;
200 Op->EndLoc = S;
201 return Op;
206 auto Op = make_unique<BPFOperand>(Register);
207 Op->Reg.RegNum = RegNo;
208 Op->StartLoc = S;
209 Op->EndLoc = E;
210 return Op;
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| SimpleConstraintManager.cpp | 143 BinaryOperator::Opcode op = SE->getOpcode(); local
144 if (BinaryOperator::isComparisonOp(op)) {
146 op = BinaryOperator::negateComparisonOp(op);
148 return assumeSymRel(state, SE->getLHS(), op, SE->getRHS());
159 BinaryOperator::Opcode Op = SSE->getOpcode();
160 assert(BinaryOperator::isComparisonOp(Op));
170 Op = BinaryOperator::reverseComparisonOp(Op);
172 Op = BinaryOperator::negateComparisonOp(Op)
[all...] |
| /external/deqp-deps/glslang/SPIRV/ |
| SPVRemapper.h | 150 typedef std::function<bool(spv::Op, unsigned start)> instfn_t;
173 bool isConstOp(spv::Op opCode) const;
174 bool isTypeOp(spv::Op opCode) const;
175 bool isStripOp(spv::Op opCode) const;
176 bool isFlowCtrl(spv::Op opCode) const;
177 range_t literalRange(spv::Op opCode) const;
178 range_t typeRange(spv::Op opCode) const;
179 range_t constRange(spv::Op opCode) const;
185 spv::Op asOpCode(unsigned word) const { return opOpCode(spv[word]); }
193 static spv::Op opOpCode(spirword_t data) { return spv::Op(data & spv::OpCodeMask);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 514 O << "/*Missing OP" << OpNo << "*/";
518 const MCOperand &Op = MI->getOperand(OpNo);
519 if (Op.isReg()) {
520 printRegOperand(Op.getReg(), O, MRI);
521 } else if (Op.isImm()) {
529 printImmediate32(Op.getImm(), STI, O);
535 printImmediate64(Op.getImm(), STI, O);
541 printImmediate16(Op.getImm(), STI, O);
545 printImmediateV216(Op.getImm(), STI, O);
549 O << formatDec(Op.getImm())
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 738 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
740 switch (Op.getOpcode()) {
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | 202 for (const SDValue &Op : N->op_values()) {
203 if (Op.isUndef())
215 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op)) {
218 } else if (ConstantFPSDNode *CFPN = dyn_cast<ConstantFPSDNode>(Op)) {
235 for (const SDValue &Op : N->op_values()) {
236 if (Op.isUndef())
238 if (!isa<ConstantSDNode>(Op))
248 for (const SDValue &Op : N->op_values()) {
249 if (Op.isUndef())
251 if (!isa<ConstantFPSDNode>(Op))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| Instructions.cpp | 125 Op<-1>().set(0);
144 if (NumOps < 2) NumOps = 2; // 2 op PHI nodes are VERY common.
261 Op<-1>() = Func;
283 Op<-1>() = Func;
516 Op<-3>() = Fn;
517 Op<-2>() = IfNormal;
518 Op<-1>() = IfException;
593 Op<0>() = RI.Op<0>();
602 Op<0>() = retVal
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 166 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
167 switch (Op.getOpcode())
169 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
170 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
171 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
172 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
173 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
174 case ISD::LOAD: return LowerLOAD(Op, DAG);
175 case ISD::STORE: return LowerSTORE(Op, DAG);
176 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 163 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
165 switch (Op.getOpcode()) {
166 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
167 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
168 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
169 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
170 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
689 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
690 SDValue Chain = Op.getOperand(0);
691 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get()
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| CodeGenInstruction.cpp | 155 CGIOperandList::ParseOperandName(const std::string &Op, bool AllowWholeOp) {
156 if (Op.empty() || Op[0] != '$')
157 throw TheDef->getName() + ": Illegal operand name: '" + Op + "'";
159 std::string OpName = Op.substr(1);
167 throw TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'";
178 " whole operand part of complex operand '" + Op + "'";
187 throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'";
195 throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'";
209 std::pair<unsigned,unsigned> Op = Ops.ParseOperandName(Name, false)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Analysis/ |
| ScalarEvolutionExpressions.h | 71 const SCEV *Op;
75 unsigned SCEVTy, const SCEV *op, Type *ty);
78 const SCEV *getOperand() const { return Op; }
95 const SCEV *op, Type *ty);
110 const SCEV *op, Type *ty);
125 const SCEV *op, Type *ty);
523 for (const auto *Op : cast<SCEVNAryExpr>(S)->operands())
524 push(Op);
628 for (auto *Op : Expr->operands()) {
629 Operands.push_back(((SC*)this)->visit(Op));
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| AVRISelDAGToDAG.cpp | 39 bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp);
44 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
65 bool AVRDAGToDAGISel::SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
67 SDLoc dl(Op);
108 MVT VT = cast<MemSDNode>(Op)->getMemoryVT().getSimpleVT();
203 bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
213 SDLoc dl(Op);
216 const RegisterSDNode *RegNode = dyn_cast<RegisterSDNode>(Op);
221 OutOps.push_back(Op);
225 if (Op->getOpcode() == ISD::FrameIndex)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 175 const RTLIB::Libcall Op;
235 setLibcallName(LC.Op, LC.Name);
237 setCmpLibcallCC(LC.Op, LC.Cond);
259 const RTLIB::Libcall Op;
348 setLibcallName(LC.Op, LC.Name);
349 setLibcallCallingConv(LC.Op, LC.CC);
351 setCmpLibcallCC(LC.Op, LC.Cond);
358 const RTLIB::Libcall Op;
371 setLibcallName(LC.Op, LC.Name);
372 setLibcallCallingConv(LC.Op, LC.CC)
[all...] |
| /external/eigen/Eigen/src/SparseCore/ |
| SparseUtil.h | 21 #define EIGEN_SPARSE_INHERIT_ASSIGNMENT_OPERATOR(Derived, Op) \
23 EIGEN_STRONG_INLINE Derived& operator Op(const Eigen::SparseMatrixBase<OtherDerived>& other) \
25 return Base::operator Op(other.derived()); \
27 EIGEN_STRONG_INLINE Derived& operator Op(const Derived& other) \
29 return Base::operator Op(other); \
32 #define EIGEN_SPARSE_INHERIT_SCALAR_ASSIGNMENT_OPERATOR(Derived, Op) \
34 EIGEN_STRONG_INLINE Derived& operator Op(const Other& scalar) \
36 return Base::operator Op(scalar); \
|
| /external/llvm/include/llvm/MC/ |
| MCWinEH.h | 27 Instruction(unsigned Op, MCSymbol *L, unsigned Reg, unsigned Off)
28 : Label(L), Offset(Off), Register(Reg), Operation(Op) {}
|
