/device/linaro/bootloader/edk2/Omap35xxPkg/MmcHostDxe/ |
MmcHostDxe.c | 382 MmioOr32 (MMCHS_SYSCTL, SRC);
383 while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
MachineSink.cpp | 121 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); 123 if (SRC != DRC)
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MachineVerifier.cpp | 753 const TargetRegisterClass *SRC = 755 if (!SRC) { 761 if (RC != SRC) { [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
RegisterInfoEmitter.cpp | [all...] |
/cts/tests/tests/uirendering/src/android/uirendering/cts/testclasses/ |
XfermodeTest.java | 49 * 2) Only src, dst empty 50 * 3) Both src + dst 51 * 4) Only dst, src empty 94 { PorterDuff.Mode.SRC, new int[] {
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/developers/build/prebuilts/gradle/DrawableTinting/Application/src/main/java/com/example/android/drawabletinting/ |
DrawableTintingFragment.java | 148 PorterDuff.Mode.SRC,
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/developers/samples/android/ui/DrawableTinting/Application/src/main/java/com/example/android/drawabletinting/ |
DrawableTintingFragment.java | 148 PorterDuff.Mode.SRC,
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/development/samples/ApiDemos/src/com/example/android/apis/graphics/ |
Xfermodes.java | 47 // create a bitmap with a rect, used for the "src" image 75 new PorterDuffXfermode(PorterDuff.Mode.SRC), 93 "Clear", "Src", "Dst", "SrcOver", 142 // draw the src/dst example into our offscreen bitmap
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/development/samples/browseable/DrawableTinting/src/com.example.android.drawabletinting/ |
DrawableTintingFragment.java | 148 PorterDuff.Mode.SRC,
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/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
Omap3530MMCHS.h | 108 #define SRC BIT25
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
SIRegisterInfo.h | 153 /// \returns A VGPR reg class with the same width as \p SRC 155 const TargetRegisterClass *SRC) const; 157 /// \returns A SGPR reg class with the same width as \p SRC
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/external/swiftshader/third_party/LLVM/lib/ExecutionEngine/Interpreter/ |
Execution.cpp | 812 GenericValue SRC = getOperandValue(I.getPointerOperand(), SF); 813 GenericValue *Ptr = (GenericValue*)GVTOP(SRC); 824 GenericValue SRC = getOperandValue(I.getPointerOperand(), SF); 825 StoreValueToMemory(Val, (GenericValue *)GVTOP(SRC), 853 case Intrinsic::vacopy: // va_copy: dest = src 892 GenericValue SRC = getOperandValue(SF.Caller.getCalledValue(), SF); 893 callFunction((Function*)GVTOP(SRC), ArgVals); [all...] |
/external/llvm/lib/CodeGen/ |
MachineSink.cpp | 170 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); 172 if (SRC != DRC)
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/external/openssh/contrib/aix/ |
buildbff.sh | 261 # Set startup command depending on SRC support 264 echo Creating SRC sshd subsystem. 274 # If migrating to or from SRC, change previous startup command
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/bionic/libc/arch-x86/atom/string/ |
ssse3-strlcat-atom.S | 81 #define SRC DST+8 82 #define LEN SRC+4 111 movl SRC(%esp), %ecx 842 movl SRC(%esp), %ecx
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/cts/apps/CtsVerifier/src/com/android/cts/verifier/sensors/ |
MotionIndicatorView.java | 134 mEraserPaint.setXfermode(new PorterDuffXfermode(PorterDuff.Mode.SRC));
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/external/setupdesign/main/src/com/google/android/setupdesign/ |
GlifPatternDrawable.java | 168 tempPaint.setXfermode(new PorterDuffXfermode(PorterDuff.Mode.SRC));
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/external/swiftshader/third_party/LLVM/utils/TableGen/ |
CodeGenRegisters.cpp | 303 ListInit *SRC = R->getValueAsListInit("SubRegClasses"); 304 for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
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RegisterInfoEmitter.cpp | 804 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx)) 805 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName() 806 << " -> " << SRC->getName() << "\n";
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/external/llvm/utils/TableGen/ |
RegisterInfoEmitter.cpp | [all...] |
/external/antlr/gunit/src/main/antlr3/org/antlr/gunit/swingui/parsers/ |
ANTLRv3.g | 466 ( ' $ANTLR ' SRC // src directive 601 SRC : 'src' ' ' file=ACTION_STRING_LITERAL ' ' line=INT
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/external/antlr/tool/src/main/antlr3/org/antlr/grammar/v3/ |
ANTLRv3.g | 473 ( ' $ANTLR ' SRC // src directive 608 SRC : 'src' ' ' file=ACTION_STRING_LITERAL ' ' line=INT
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/external/llvm/lib/Target/AMDGPU/ |
SIRegisterInfo.cpp | 567 .addReg(TmpReg, RegState::Kill) // src 640 TII->getNamedOperand(*MI, AMDGPU::OpName::src), 730 const TargetRegisterClass *SRC) const { 731 switch (SRC->getSize()) { [all...] |
SIInstrInfo.cpp | 603 .addReg(SrcReg, getKillRegState(isKill)) // src 625 .addReg(SrcReg, getKillRegState(isKill)) // src [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
MachineSink.cpp | 206 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); 208 if (SRC != DRC) [all...] |