| /external/llvm/lib/Target/X86/ |
| X86IntrinsicsInfo.h | [all...] |
| X86ISelDAGToDAG.cpp | 336 User->getOpcode() == X86ISD::SUB ||
337 User->getOpcode() == ISD::SUB) {
339 // Find the other operand of the add/sub.
414 case X86ISD::SUB:
[all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb-instructions.s | 71 @ CHECK: sub sp, #8 @ encoding: [0x82,0xb0]
72 @ CHECK: sub sp, #8 @ encoding: [0x82,0xb0]
598 @ SUB (immediate)
610 @ SUB (SP minus immediate)
612 sub sp, #12
613 sub sp, sp, #508
615 @ CHECK: sub sp, #12 @ encoding: [0x83,0xb0]
616 @ CHECK: sub sp, #508 @ encoding: [0xff,0xb0]
620 @ SUB (register)
|
| /external/pcre/dist2/src/sljit/ |
| sljitNativeX86_64.c | 188 FAIL_IF(emit_non_cum_binary(compiler, BINARY_OPCODE(SUB),
190 FAIL_IF(emit_non_cum_binary(compiler, BINARY_OPCODE(SUB),
206 FAIL_IF(emit_non_cum_binary(compiler, BINARY_OPCODE(SUB),
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| basic-thumb-instructions.s | 547 @ SUB (immediate)
559 @ SUB (SP minus immediate)
561 sub sp, #12
562 sub sp, sp, #508
564 @ CHECK: sub sp, #12 @ encoding: [0x83,0xb0]
565 @ CHECK: sub sp, #508 @ encoding: [0xff,0xb0]
569 @ SUB (register)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 343 User->getOpcode() == X86ISD::SUB ||
344 User->getOpcode() == ISD::SUB) {
346 // Find the other operand of the add/sub.
520 case X86ISD::SUB:
[all...] |
| X86TargetTransformInfo.cpp | 217 { ISD::SUB, MVT::v2i64, 4 },
271 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info);
295 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence
297 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence
313 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence
315 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence
333 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence
335 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence
337 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence
339 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequenc
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| basic-thumb-instructions.s | 71 @ CHECK: sub sp, #8 @ encoding: [0x82,0xb0]
72 @ CHECK: sub sp, #8 @ encoding: [0x82,0xb0]
598 @ SUB (immediate)
610 @ SUB (SP minus immediate)
612 sub sp, #12
613 sub sp, sp, #508
615 @ CHECK: sub sp, #12 @ encoding: [0x83,0xb0]
616 @ CHECK: sub sp, #508 @ encoding: [0xff,0xb0]
620 @ SUB (register)
|
| /external/tensorflow/tensorflow/core/kernels/ |
| resource_variable_ops.cc | 530 AssignUpdateVariableOp<Eigen::ThreadPoolDevice, type, SUB>);
546 AssignUpdateVariableOp<GPUDevice, type, SUB>);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | 278 case ISD::SUB: {
669 } else if (Addr.getOpcode() == ISD::SUB) {
670 // sub C, x -> add (sub 0, x), C
676 // XXX - This is kind of hacky. Create a dummy sub node so we can check
679 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
682 if (isDSOffsetLegal(Sub, ByteOffset, 16)) {
736 } else if (Addr.getOpcode() == ISD::SUB) {
737 // sub C, x -> add (sub 0, x),
[all...] |
| AMDGPUISelLowering.cpp | 376 setOperationAction(ISD::SUB, VT, Expand);
525 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 128 setTargetDAGCombine(ISD::SUB);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 123 case ISD::SUB:
161 // If the result is null then the sub-method took care of registering it.
382 ISD::SUB, dl, NVT, Op,
551 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
744 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
[all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 604 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
628 if (N.getOpcode() == ISD::SUB)
662 AddSub = ARM_AM::sub;
677 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
691 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
717 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
773 AddSub = ARM_AM::sub;
788 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
810 if (N.getOpcode() != ISD::SUB) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 280 setOperationAction(ISD::SUB, MVT::i8, Custom);
281 setOperationAction(ISD::SUB, MVT::i64, Legal);
408 // add/sub are legal for all supported vector VT's.
410 setOperationAction(ISD::SUB, VT, Legal);
707 DAG.getNode(ISD::SUB, dl, MVT::i32,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 105 case ISD::SUB:
141 // If the result is null then the sub-method took care of registering it.
317 return DAG.getNode(ISD::SUB, dl, NVT, Op,
457 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
620 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
[all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 100 setOperationAction(ISD::SUB, MVT::i64, Custom);
217 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
241 case ISD::SUB:
721 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 99 setOperationAction(ISD::SUB, MVT::i64, Custom);
183 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
203 case ISD::SUB:
708 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 97 setOperationAction(ISD::SUB, MVT::i64, Custom);
214 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
238 case ISD::SUB:
711 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
[all...] |
| /external/v8/src/interpreter/ |
| bytecode-array-builder.cc | 356 case Token::Value::SUB:
401 case Token::Value::SUB:
452 case Token::Value::SUB:
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm_vixl.cc | 117 case SUB:
|
| /external/libxaac/decoder/armv7/ |
| ixheaacd_sbr_qmfsyn64_winadd.s | 177 SUB R6, R6, #2
|
| /external/libxaac/decoder/armv8/ |
| ixheaacd_sbr_qmf_analysis32_neon.s | 52 ////SUB x6, x6, x9
217 SUB x5, x5, #1
|
