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  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp     [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/ARM/
ARMISelLowering.cpp     [all...]
  /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
X86GenDAGISel.inc     [all...]
  /external/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 308 setOperationAction(ISD::SUB, VT, Legal);
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 330 setOperationAction(ISD::SUB, VT, Legal);
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  /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
PPCISelLowering.cpp 295 // add/sub are legal for all supported vector VT's.
297 setOperationAction(ISD::SUB , VT, Legal);
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  /external/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 220 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence.
221 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence.
345 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence.
346 { ISD::SRA, MVT::v4i64, 2*12 }, // srl/xor/sub sequence.
375 { ISD::SUB, MVT::v8i32, 4 },
377 { ISD::SUB, MVT::v4i64, 4 },
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  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAG.cpp 602 if (Shl_0.getOpcode() == ISD::SUB) {
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  /external/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 263 case ISD::SUB:
650 // For sub-byte element sizes, this ends up with 0 stride between elements,
    [all...]
SelectionDAG.cpp     [all...]
LegalizeVectorTypes.cpp 126 case ISD::SUB:
140 // If R is null, the sub-method took care of registering the result.
464 // If the result is null, the sub-method took care of registering results etc.
467 // If the result is N, the sub-method updated N in place. Tell the legalizer
668 case ISD::SUB:
703 // If Lo/Hi is null, the sub-method took care of registering results etc.
    [all...]
  /external/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp     [all...]
  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_vertprog.c 10 on the rights to use, copy, modify, merge, publish, distribute, sub
95 OPN(SUB, 2),
    [all...]
  /external/mesa3d/src/mesa/main/
shader_query.cpp 63 DECL_RESOURCE_FUNC(SUB, gl_subroutine_function);
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  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
X86ISelLowering.h 209 /// Combined add and sub on an FP vector.
229 // Integer add/sub with unsigned saturation.
233 // Integer add/sub with signed saturation.
240 /// Integer horizontal add/sub.
244 /// Floating point horizontal add/sub.
352 ADD, SUB, ADC, SBB, SMUL,
    [all...]
  /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
LegalizeVectorTypes.cpp 109 case ISD::SUB:
120 // If R is null, the sub-method took care of registering the result.
328 // If the result is null, the sub-method took care of registering results etc.
331 // If the result is N, the sub-method updated N in place. Tell the legalizer
475 case ISD::SUB:
497 // If Lo/Hi is null, the sub-method took care of registering results etc.
    [all...]
SelectionDAG.cpp     [all...]
SelectionDAGBuilder.cpp     [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
SelectionDAG.cpp     [all...]
  /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
ARMGenDAGISel.inc     [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 556 setOperationAction(ISD::SUB, MVT::v2i16, Legal);
580 setOperationAction(ISD::SUB, MVT::v4i16, Custom);
620 setTargetDAGCombine(ISD::SUB);
    [all...]
  /external/mesa3d/src/gallium/state_trackers/nine/
nine_shader.c 8 * on the rights to use, copy, modify, merge, publish, distribute, sub
    [all...]
  /external/llvm/test/MC/ARM/
v8_IT_manual.s 54 @ SUB reg, encoding T1
58 @ SUB reg, encoding T2 (32-bit)
62 @ SUB imm, encoding T1
66 @ SUB imm, encoding T2
70 @ SUB imm, encoding T3 (32-bit)
74 @ SUB imm, encoding T4 (32-bit)
78 @ SUB SP-imm, encoding T1
82 @ SUB SP-imm, encoding T3 (32-bit)
86 @ SUB SP-imm, encoding T4 (32-bit)
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  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 153 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
554 // add/sub are legal for all supported vector VT's.
556 setOperationAction(ISD::SUB, VT, Legal);
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
v8_IT_manual.s 54 @ SUB reg, encoding T1
58 @ SUB reg, encoding T2 (32-bit)
62 @ SUB imm, encoding T1
66 @ SUB imm, encoding T2
70 @ SUB imm, encoding T3 (32-bit)
74 @ SUB imm, encoding T4 (32-bit)
78 @ SUB SP-imm, encoding T1
82 @ SUB SP-imm, encoding T3 (32-bit)
86 @ SUB SP-imm, encoding T4 (32-bit)
    [all...]

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