| /external/libavc/encoder/arm/ |
| ime_distortion_metrics_a9q.s | 28 @* between two macro/sub blocks of identical dimensions
290 sub r0, r0, r2, lsl #3
292 sub r1, r1, r3, lsl #3
542 @* @brief computes distortion (SAD) for sub-pel motion estimation
575 sub r4, r1, #1 @ x left
576 sub r5, r2, r10 @ y top
578 sub r6, r3, #1 @ xy left
579 sub r7, r3, r10 @ xy top
581 sub r8, r7, #1 @ xy top-left
795 sub r4, r0, #0x01 @r4 = left_pt
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| LegalizeFloatTypes.cpp | 115 // If R is null, the sub-method took care of registering the result.
291 Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, dl, LVT));
440 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 102 // If R is null, the sub-method took care of registering the result.
209 Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, LVT));
343 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
595 // If the result is null, the sub-method took care of registering results etc.
598 // If the result is N, the sub-method updated N in place. Tell the legalizer
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| LegalizeFloatTypes.cpp | 294 Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, dl, LVT));
443 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
[all...] |
| /external/compiler-rt/lib/msan/tests/ |
| msan_test.cc | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| ARMGenFastISel.inc | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 503 setTargetDAGCombine(ISD::SUB);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| assembler_arm.cc | 201 // Moved to ARM32::AssemberARM32::sub()
202 void Assembler::sub(Register rd, Register rn, Operand o, Condition cond) {
203 EmitType01(cond, o.type(), SUB, 0, rn, rd, o);
226 // Moved to ARM32::AssemberARM32::sub()
228 EmitType01(cond, o.type(), SUB, 1, rn, rd, o);
403 sub(rd, ra, Operand(IP), cond);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| AArch64GenDAGISel.inc | [all...] |
| /art/compiler/optimizing/ |
| code_generator_arm_vixl.cc | [all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| MipsGenInstrInfo.inc | [all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| basic-thumb2-instructions.s | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.cc | 1131 void Assembler::sub(const Register& rd, function in class:v8::internal::Assembler
[all...] |
| simulator-arm64.cc | 818 if ((instr->Mask(AddSubOpMask) == SUB) || instr->Mask(AddSubOpMask) == SUBS) {
[all...] |
| /external/vixl/src/aarch64/ |
| simulator-aarch64.cc | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/guice/lib/build/ |
| bnd-0.0.384.jar | |
| cglib-3.2.6.jar | |
