| /device/linaro/bootloader/edk2/SecurityPkg/Tcg/Opal/OpalPasswordSmm/ |
| OpalIdeMode.h | 54 #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3
|
| /device/linaro/bootloader/edk2/MdePkg/Include/Guid/ |
| Cper.h | 158 #define EFI_ERROR_SECTION_FLAGS_ERROR_THRESHOLD_EXCEEDED BIT3
242 #define EFI_GENERIC_ERROR_PROC_OPERATION_VALID BIT3
296 #define EFI_GENERIC_ERROR_PROC_FLAGS_CORRECTED BIT3
373 #define EFI_CACHE_CHECK_CONTEXT_CORRUPT_VALID BIT3
426 #define EFI_TLB_CHECK_CONTEXT_CORRUPT_VALID BIT3
477 #define EFI_BUS_CHECK_CONTEXT_CORRUPT_VALID BIT3
552 #define EFI_MS_CHECK_PRECISE_IP_VALID BIT3
600 #define EFI_IA32_X64_ERROR_PROC_RESPONDER_ID_VALID BIT3
787 #define EFI_PLATFORM_MEMORY_NODE_VALID BIT3
863 #define EFI_PLATFORM_MEMORY2_NODE_VALID BIT3
[all...] |
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/ |
| PL180Mci.h | 86 #define MCI_STATUS_CMD_DATATIMEOUT BIT3
138 #define MCI_DATACTL_DMA_ENABLE BIT3
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| /device/linaro/bootloader/edk2/ShellPkg/Include/Library/ |
| HandleParsingLib.h | 145 #define HR_DEVICE_DRIVER BIT3 // device driver (hybrid?)
154 #define HR_VALID_MASK (BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7|BIT8|BIT9|BIT10|BIT11)
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| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| Lan9118DxeHw.h | 135 #define RXSTATUS_MII_ERROR BIT3 // Receive error during interception
210 #define MPTCTRL_PME_IND BIT3 // Signal type of PME (refer to Spec)
232 #define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability
272 #define MACCR_TX_EN BIT3 // Enable Transmitter bit
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| /device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/ |
| IScsiBootFirmwareTable.h | 158 #define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_RCHAP BIT3
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| /device/linaro/bootloader/edk2/OvmfPkg/Include/Library/ |
| QemuFwCfgLib.h | 39 #define FW_CFG_DMA_CTL_SELECT BIT3
|
| /device/linaro/bootloader/edk2/OvmfPkg/Library/PciHostBridgeLib/ |
| XenSupport.c | 132 if ((Value & BIT3) == BIT3) {
152 if ((Value & BIT3) == BIT3) {
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
| CommonIncludes.h | 113 #define BIT3 0x00000008
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| meminit.c | 557 isbM32m(DDRPHY, (B01LATCTL1 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // Launch Time: ODT, DIFFAMP, ODT, DIFFAMP
577 isbM32m(DDRPHY, (B0LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
578 isbM32m(DDRPHY, (B1LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
587 isbM32m(DDRPHY, (B0VREFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), ((0x03<<2)|(0x0<<1)|(0x0<<0)), ((BIT7|BIT6|BIT5|BIT4|BIT3|BIT2)|BIT1|BIT0)); // Internal Vref Code, Enable#, Ext_or_Int (1=Ext)
588 isbM32m(DDRPHY, (B1VREFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), ((0x03<<2)|(0x0<<1)|(0x0<<0)), ((BIT7|BIT6|BIT5|BIT4|BIT3|BIT2)|BIT1|BIT0)); // Internal Vref Code, Enable#, Ext_or_Int (1=Ext)
599 isbM32m(DDRPHY, (CMDRCOMPODT + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x03<<5)|(0x03<<0)), ((BIT9|BIT8|BIT7|BIT6|BIT5)|(BIT4|BIT3|BIT2|BIT1|BIT0)));
602 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
603 isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT_for_PM_MSG_gt0, MDLL Turn On
604 isbM32m(DDRPHY, (CMDPMDLYREG2 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // MPLL Divider Reset Delays
605 isbM32m(DDRPHY, (CMDPMDLYREG1 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn Off Delays: VREG, Staggered MDLL, MDLL, PI
[all...] |
| /device/linaro/bootloader/edk2/CorebootPayloadPkg/Library/PciHostBridgeLib/ |
| PciHostBridgeSupport.c | 248 if ((Value & BIT3) == BIT3) {
271 if ((Value & BIT3) == BIT3) {
|
| /device/linaro/bootloader/edk2/IntelSiliconPkg/Include/IndustryStandard/ |
| IgdOpRegion.h | 26 #define IGD_OPREGION_HEADER_MBOX4 BIT3
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| Omap3530Dma.h | 112 #define DMA4_CSR_FRAME BIT3
|
| /device/linaro/bootloader/edk2/OptionRomPkg/AtapiPassThruDxe/ |
| AtapiPassThru.h | 76 #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3
213 #define MCR_ERR BIT3 ///< Media Change Requested
230 #define HS3 BIT3
247 #define DRQ BIT3 ///< Data Request
[all...] |
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchRegs.h | 49 #define BIT3 0x0008
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/ |
| UartInit.c | 42 #define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/VlvPlatformInitDxe/ |
| IgdOpRegion.h | 74 #define HD_MBOX4 BIT3
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/ |
| SDController.c | 205 if (ErrorCode & BIT3) {
312 Data |= BIT3; // Enable 1.8V Signaling
670 Data = (CommandIndex << 8) | BIT1 | BIT4| BIT3;
676 Data = (CommandIndex << 8) | BIT0 | BIT1 | BIT4| BIT3;
681 Data = (CommandIndex << 8) | BIT0 | BIT3;
1056 Data |= (BIT1 | BIT3 | BIT0);
1061 Data |= (BIT2 | BIT3 | BIT0);
1066 Data |= (BIT1 | BIT2 | BIT3 | BIT0);
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Block/DwUfsHcDxe/ |
| DwUfsHcDxe.h | 94 #define UFS_HC_HCS_UCRDY BIT3
100 #define UFS_HC_CAP_NUTRS (BIT0 | BIT1 | BIT2 | BIT3 | BIT4)
|
| /device/linaro/bootloader/edk2/ArmPkg/Include/Chipset/ |
| ArmV7Mmu.h | 20 #define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3
22 #define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)
|
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Library/Tpm12DeviceLibInfineonI2c/ |
| TisPc.c | 69 #define TIS_PC_ACC_SEIZE BIT3
99 #define TIS_PC_STS_EXPECT BIT3
|
| /device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/ |
| StmApi.h | 564 #define DOMAIN_CONFIDENTIALITY BIT3
630 #define STM_RSC_MSR BIT3
[all...] |
| /device/linaro/bootloader/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/ |
| SmmCpuFeaturesLib.c | 235 // make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set before
241 if ((FeatureControl & BIT3) == 0) {
243 AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL, FeatureControl | BIT3);
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| BoardFeatures.h | 50 #define B_BOARD_FEATURES_SIO_NO_COM1 BIT3
144 #define B_BOARD_FEATURES_AA_NOT_FOUND BIT3
|
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Usb/DwUsbDxe/ |
| DwUsbDxe.h | 51 #define DW_DC_INTERRUPT_SUSP BIT3
71 #define DW_ENDPOINT_TYPE_ENABLE BIT3
81 #define DW_CTRL_FUNCTION_VENDP BIT3
227 #define GINTSTS_SOF BIT3
401 #define DXEPMSK_TIMEOUTMSK BIT3
|
