1 /** @file 2 Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180. 3 4 Copyright (c) 2011-2012, ARM Limited. All rights reserved. 5 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 16 #ifndef __PL180_MCI_H 17 #define __PL180_MCI_H 18 19 #include <Uefi.h> 20 21 #include <Protocol/MmcHost.h> 22 23 #include <Library/UefiLib.h> 24 #include <Library/DebugLib.h> 25 #include <Library/UefiBootServicesTableLib.h> 26 #include <Library/IoLib.h> 27 #include <Library/TimerLib.h> 28 #include <Library/PcdLib.h> 29 30 #define PL180_MCI_DXE_VERSION 0x10 31 32 #define MCI_SYSCTL FixedPcdGet32 (PcdPL180MciBaseAddress) 33 34 #define MCI_POWER_CONTROL_REG (MCI_SYSCTL + 0x000) 35 #define MCI_CLOCK_CONTROL_REG (MCI_SYSCTL + 0x004) 36 #define MCI_ARGUMENT_REG (MCI_SYSCTL + 0x008) 37 #define MCI_COMMAND_REG (MCI_SYSCTL + 0x00C) 38 #define MCI_RESPCMD_REG (MCI_SYSCTL + 0x010) 39 #define MCI_RESPONSE3_REG (MCI_SYSCTL + 0x014) 40 #define MCI_RESPONSE2_REG (MCI_SYSCTL + 0x018) 41 #define MCI_RESPONSE1_REG (MCI_SYSCTL + 0x01C) 42 #define MCI_RESPONSE0_REG (MCI_SYSCTL + 0x020) 43 #define MCI_DATA_TIMER_REG (MCI_SYSCTL + 0x024) 44 #define MCI_DATA_LENGTH_REG (MCI_SYSCTL + 0x028) 45 #define MCI_DATA_CTL_REG (MCI_SYSCTL + 0x02C) 46 #define MCI_DATA_COUNTER (MCI_SYSCTL + 0x030) 47 #define MCI_STATUS_REG (MCI_SYSCTL + 0x034) 48 #define MCI_CLEAR_STATUS_REG (MCI_SYSCTL + 0x038) 49 #define MCI_INT0_MASK_REG (MCI_SYSCTL + 0x03C) 50 #define MCI_INT1_MASK_REG (MCI_SYSCTL + 0x040) 51 #define MCI_SELECT_REG (MCI_SYSCTL + 0x044) 52 #define MCI_FIFOCOUNT_REG (MCI_SYSCTL + 0x048) 53 #define MCI_FIFO_REG (MCI_SYSCTL + 0x080) 54 #define MCI_PERIPH_ID_REG0 (MCI_SYSCTL + 0xFE0) 55 #define MCI_PERIPH_ID_REG1 (MCI_SYSCTL + 0xFE4) 56 #define MCI_PERIPH_ID_REG2 (MCI_SYSCTL + 0xFE8) 57 #define MCI_PERIPH_ID_REG3 (MCI_SYSCTL + 0xFEC) 58 #define MCI_PCELL_ID_REG0 (MCI_SYSCTL + 0xFF0) 59 #define MCI_PCELL_ID_REG1 (MCI_SYSCTL + 0xFF4) 60 #define MCI_PCELL_ID_REG2 (MCI_SYSCTL + 0xFF8) 61 #define MCI_PCELL_ID_REG3 (MCI_SYSCTL + 0xFFC) 62 63 #define MCI_PERIPH_ID0 0x80 64 #define MCI_PERIPH_ID1 0x11 65 #define MCI_PERIPH_ID2 0x04 66 #define MCI_PERIPH_ID3 0x00 67 #define MCI_PCELL_ID0 0x0D 68 #define MCI_PCELL_ID1 0xF0 69 #define MCI_PCELL_ID2 0x05 70 #define MCI_PCELL_ID3 0xB1 71 72 #define MCI_POWER_OFF 0 73 #define MCI_POWER_UP BIT1 74 #define MCI_POWER_ON (BIT1 | BIT0) 75 #define MCI_POWER_OPENDRAIN BIT6 76 #define MCI_POWER_ROD BIT7 77 78 #define MCI_CLOCK_ENABLE BIT8 79 #define MCI_CLOCK_POWERSAVE BIT9 80 #define MCI_CLOCK_BYPASS BIT10 81 #define MCI_CLOCK_WIDEBUS BIT11 82 83 #define MCI_STATUS_CMD_CMDCRCFAIL BIT0 84 #define MCI_STATUS_CMD_DATACRCFAIL BIT1 85 #define MCI_STATUS_CMD_CMDTIMEOUT BIT2 86 #define MCI_STATUS_CMD_DATATIMEOUT BIT3 87 #define MCI_STATUS_CMD_TX_UNDERRUN BIT4 88 #define MCI_STATUS_CMD_RXOVERRUN BIT5 89 #define MCI_STATUS_CMD_RESPEND BIT6 90 #define MCI_STATUS_CMD_SENT BIT7 91 #define MCI_STATUS_CMD_DATAEND BIT8 92 #define MCI_STATUS_CMD_START_BIT_ERROR BIT9 93 #define MCI_STATUS_CMD_DATABLOCKEND BIT10 94 #define MCI_STATUS_CMD_ACTIVE BIT11 95 #define MCI_STATUS_CMD_TXACTIVE BIT12 96 #define MCI_STATUS_CMD_RXACTIVE BIT13 97 #define MCI_STATUS_CMD_TXFIFOHALFEMPTY BIT14 98 #define MCI_STATUS_CMD_RXFIFOHALFFULL BIT15 99 #define MCI_STATUS_CMD_TXFIFOFULL BIT16 100 #define MCI_STATUS_CMD_RXFIFOFULL BIT17 101 #define MCI_STATUS_CMD_TXFIFOEMPTY BIT18 102 #define MCI_STATUS_CMD_RXFIFOEMPTY BIT19 103 #define MCI_STATUS_CMD_TXDATAAVAILBL BIT20 104 #define MCI_STATUS_CMD_RXDATAAVAILBL BIT21 105 106 #define MCI_STATUS_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND) 107 #define MCI_STATUS_RXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND) 108 #define MCI_STATUS_READ_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \ 109 | MCI_STATUS_CMD_DATATIMEOUT \ 110 | MCI_STATUS_CMD_RXOVERRUN \ 111 | MCI_STATUS_CMD_START_BIT_ERROR ) 112 #define MCI_STATUS_WRITE_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \ 113 | MCI_STATUS_CMD_DATATIMEOUT \ 114 | MCI_STATUS_CMD_TX_UNDERRUN ) 115 #define MCI_STATUS_CMD_ERROR ( MCI_STATUS_CMD_CMDCRCFAIL \ 116 | MCI_STATUS_CMD_CMDTIMEOUT \ 117 | MCI_STATUS_CMD_START_BIT_ERROR ) 118 119 #define MCI_CLR_CMD_STATUS ( MCI_STATUS_CMD_RESPEND \ 120 | MCI_STATUS_CMD_SENT \ 121 | MCI_STATUS_CMD_ERROR ) 122 123 #define MCI_CLR_READ_STATUS ( MCI_STATUS_RXDONE \ 124 | MCI_STATUS_READ_ERROR ) 125 126 #define MCI_CLR_WRITE_STATUS ( MCI_STATUS_TXDONE \ 127 | MCI_STATUS_WRITE_ERROR ) 128 129 #define MCI_CLR_ALL_STATUS (BIT11 - 1) 130 131 #define MCI_DATACTL_DISABLE_MASK 0xFE 132 #define MCI_DATACTL_ENABLE BIT0 133 #define MCI_DATACTL_CONT_TO_CARD 0 134 #define MCI_DATACTL_CARD_TO_CONT BIT1 135 #define MCI_DATACTL_BLOCK_TRANS 0 136 #define MCI_DATACTL_STREAM_TRANS BIT2 137 #define MCI_DATACTL_DMA_DISABLED 0 138 #define MCI_DATACTL_DMA_ENABLE BIT3 139 140 #define INDX_MASK 0x3F 141 142 #define MCI_CPSM_WAIT_RESPONSE BIT6 143 #define MCI_CPSM_LONG_RESPONSE BIT7 144 #define MCI_CPSM_LONG_INTERRUPT BIT8 145 #define MCI_CPSM_LONG_PENDING BIT9 146 #define MCI_CPSM_ENABLE BIT10 147 148 #define MCI_TRACE(txt) DEBUG ((EFI_D_BLKIO, "ARM_MCI: " txt "\n")) 149 150 EFI_STATUS 151 EFIAPI 152 MciGetDriverName ( 153 IN EFI_COMPONENT_NAME_PROTOCOL *This, 154 IN CHAR8 *Language, 155 OUT CHAR16 **DriverName 156 ); 157 158 EFI_STATUS 159 EFIAPI 160 MciGetControllerName ( 161 IN EFI_COMPONENT_NAME_PROTOCOL *This, 162 IN EFI_HANDLE ControllerHandle, 163 IN EFI_HANDLE ChildHandle OPTIONAL, 164 IN CHAR8 *Language, 165 OUT CHAR16 **ControllerName 166 ); 167 168 #endif 169
