| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 79 case ISD::EXTRACT_SUBVECTOR:
593 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
595 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
[all...] |
| SelectionDAGBuilder.cpp | 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
[all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 94 case ISD::EXTRACT_SUBVECTOR:
730 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx);
[all...] |
| SelectionDAGBuilder.cpp | 426 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
460 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
718 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
[all...] |
| TargetLowering.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAGBuilder.cpp | 340 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
589 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
[all...] |
| LegalizeDAG.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 149 case ISD::EXTRACT_SUBVECTOR:
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelLowering.cpp | 98 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
702 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 253 case ISD::EXTRACT_SUBVECTOR:
487 case ISD::EXTRACT_SUBVECTOR:
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 429 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 479 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 696 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
746 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| X86GenDAGISel.inc | [all...] |
| X86GenFastISel.inc | [all...] |
