| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 137 setOperationAction(ISD::FMA, MVT::f16, Promote);
386 setOperationAction(ISD::FMA, Ty, Legal);
[all...] |
| MipsISelLowering.cpp | 445 setOperationAction(ISD::FMA, MVT::f32, Expand);
446 setOperationAction(ISD::FMA, MVT::f64, Expand);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 385 case ISD::FMA:
[all...] |
| LegalizeVectorTypes.cpp | 139 case ISD::FMA:
755 case ISD::FMA:
[all...] |
| LegalizeDAG.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 461 setOperationAction(ISD::FMA, VT, Expand);
549 case ISD::FMA:
608 // Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus
[all...] |
| R600ISelLowering.cpp | 222 setOperationAction(ISD::FMA, MVT::f32, Expand);
223 setOperationAction(ISD::FMA, MVT::f64, Expand);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 224 setOperationAction(ISD::FMA, MVT::f64, Expand);
225 setOperationAction(ISD::FMA, MVT::f32, Expand);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsISelLowering.cpp | 181 setOperationAction(ISD::FMA, MVT::f32, Expand);
182 setOperationAction(ISD::FMA, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 178 setOperationAction(ISD::FMA , MVT::f64, Legal);
184 setOperationAction(ISD::FMA , MVT::f32, Legal);
530 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
587 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 396 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
409 setOperationAction(ISD::FMA, MVT::f32, Legal);
410 setOperationAction(ISD::FMA, MVT::f64, Legal);
411 setOperationAction(ISD::FMA, MVT::f128, Expand);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| TargetLowering.h | 553 /// Return true if target always beneficiates from combining into FMA for a
554 /// given value type. This must typically return false on targets where FMA
804 case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 421 setOperationAction(ISD::FMA, VT, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 368 setOperationAction(ISD::FMA, MVT::f32, Expand);
369 setOperationAction(ISD::FMA, MVT::f64, Expand);
[all...] |
| MipsSEISelLowering.cpp | 315 setOperationAction(ISD::FMA, Ty, Legal);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 75 FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
76 cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
525 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 148 setOperationAction(ISD::FMA, MVT::f128, Expand);
271 setOperationAction(ISD::FMA, MVT::f16, Promote);
320 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
351 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
530 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 515 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
609 // NEON only has FMA instructions as of VFP4.
611 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
612 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
656 setOperationAction(ISD::FMA, MVT::f64, Expand);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 215 setOperationAction(ISD::FMA, MVT::f128, Expand);
376 setOperationAction(ISD::FMA, MVT::f16, Promote);
408 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
427 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
628 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 605 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
695 // NEON only has FMA instructions as of VFP4.
697 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
698 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | [all...] |
| /external/mesa3d/src/mesa/state_tracker/ |
| st_glsl_to_tgsi.cpp | 697 case7(FMA, FMA, UMAD, UMAD, DFMA, LAST, LAST);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 128 setOperationAction(ISD::FMA , MVT::f64, Expand);
133 setOperationAction(ISD::FMA , MVT::f32, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 575 // We don't support FMA.
576 setOperationAction(ISD::FMA, MVT::f64, Expand);
577 setOperationAction(ISD::FMA, MVT::f32, Expand);
618 setOperationAction(ISD::FMA, MVT::f80, Expand);
663 setOperationAction(ISD::FMA, VT, Expand);
[all...] |
