| /external/guice/lib/build/ |
| jarjar-1.1.jar | |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 214 setOperationAction(ISD::FREM , MVT::f64, Expand);
217 setOperationAction(ISD::FREM , MVT::f32, Expand);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/testng/lib-supplied/ |
| jarjar-issue-21.jar | |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | [all...] |
| LegalizeFloatTypes.cpp | 87 case ISD::FREM: R = SoftenFloatRes_FREM(N); break;
[all...] |
| TargetLowering.cpp | 644 case ISD::FREM:
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 234 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
274 setOperationAction(ISD::FREM , MVT::f64, Expand);
279 setOperationAction(ISD::FREM , MVT::f32, Expand);
601 setOperationAction(ISD::FREM, VT, Expand);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 124 case ISD::FREM:
748 case ISD::FREM:
[all...] |
| FastISel.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| /external/apache-commons-bcel/src/main/java/org/apache/bcel/verifier/structurals/ |
| InstConstraintVisitor.java | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 370 setOperationAction(ISD::FREM, MVT::f32, Expand);
371 setOperationAction(ISD::FREM, MVT::f64, Expand);
[all...] |
| /external/owasp/sanitizer/tools/findbugs/lib/ |
| bcel.jar | |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 447 setOperationAction(ISD::FREM, MVT::f32, Expand);
448 setOperationAction(ISD::FREM, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 154 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
176 setOperationAction(ISD::FREM , MVT::f64, Expand);
182 setOperationAction(ISD::FREM , MVT::f32, Expand);
461 setOperationAction(ISD::FREM, VT, Expand);
678 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
731 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 144 setOperationAction(ISD::FREM, VT, Expand);
485 // FIXME: Code duplication: FDIV and FREM are expanded always, see
488 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
658 setOperationAction(ISD::FREM, MVT::f64, Expand);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 205 setOperationAction(ISD::FREM, VT, Expand);
576 // FIXME: Code duplication: FDIV and FREM are expanded always, see
579 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 126 setOperationAction(ISD::FREM , MVT::f64, Expand);
131 setOperationAction(ISD::FREM , MVT::f32, Expand);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMISelLowering.cpp | 156 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
464 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
704 setOperationAction(ISD::FREM, MVT::f64, Expand);
705 setOperationAction(ISD::FREM, MVT::f32, Expand);
[all...] |
