| /device/linaro/bootloader/edk2/BeagleBoardPkg/Library/BeagleBoardLib/ |
| BeagleBoard.c | 48 MmioWrite32(GPIO6_BASE + GPIO_OE, (OldPinDir | BIT11 | BIT12 | BIT13));
52 MmioWrite32 (GPIO6_BASE + GPIO_OE, OldPinDir);
98 MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/InterruptDxe/ |
| HardwareInterrupt.c | 56 MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);
57 MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);
58 MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);
59 MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
137 MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
171 MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
239 MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
269 MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
279 MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
323 MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960Dxe/ |
| HiKey960Dxe.c | 119 MmioWrite32 (CRG_PERRSTEN2, PERRSTEN2_HKADCSSI);
122 MmioWrite32 (CRG_PERRSTDIS2, PERRSTEN2_HKADCSSI);
125 MmioWrite32 (CRG_PERDIS2, PEREN2_HKADCSSI);
127 MmioWrite32 (CRG_PEREN2, PEREN2_HKADCSSI);
146 MmioWrite32 (HKADC_WR01_DATA, HKADC_WR01_VALUE | Channel);
147 MmioWrite32 (HKADC_WR23_DATA, HKADC_WR23_VALUE);
148 MmioWrite32 (HKADC_WR45_DATA, HKADC_WR45_VALUE);
150 MmioWrite32 (HKADC_WR_NUM, HKADC_WR_NUM_VALUE);
152 MmioWrite32 (HKADC_DELAY01, HKADC_CHANNEL0_DELAY01_VALUE);
153 MmioWrite32 (HKADC_DELAY23, HKADC_DELAY23_VALUE);
[all...] |
| /device/linaro/bootloader/edk2/Omap35xxPkg/LcdGraphicsOutputDxe/ |
| LcdGraphicsOutputDxe.c | 145 MmioWrite32 (CM_ICLKEN_DSS, EN_DSS);
151 MmioWrite32 (CM_CLKSEL_DSS, 0x1000 | (LcdModes[ModeNumber].DssDivisor));
160 MmioWrite32(DSS_SYSCONFIG, DSS_SOFTRESET);
164 MmioWrite32 (DISPC_SIZE_LCD,
168 MmioWrite32 (DISPC_TIMING_H,
173 MmioWrite32 (DISPC_TIMING_V,
184 MmioWrite32(DISPC_DIVISOR, ((1 << 16) | LcdModes[ModeNumber].DispcDivisor) );
187 MmioWrite32 (DISPC_GFX_PRELD, 0x2D8);
188 MmioWrite32 (DISPC_GFX_BA0, VramBaseAddress);
189 MmioWrite32 (DISPC_GFX_SIZE,
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/ |
| I2CLib.c | 224 MmioWrite32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR), (UINT32) (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 & B_PCH_LPSS_I2C_BAR_BA));
230 MmioWrite32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR1), (UINT32) (mLpssPciDeviceList[I2cControllerIndex+1].Bar1 & B_PCH_LPSS_I2C_BAR1_BA));
242 MmioWrite32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 + R_PCH_LPIO_I2C_MEM_RESETS,(B_PCH_LPIO_I2C_MEM_RESETS_FUNC | B_PCH_LPIO_I2C_MEM_RESETS_APB));
247 MmioWrite32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 + R_PCH_LPSS_I2C_MEM_PCP,0x80020003);//No use for A0
296 MmioWrite32 ( mI2CBaseAddress + R_IC_ENABLE, 0 );
325 MmioWrite32 (mI2CBaseAddress + R_IC_ENABLE, 1);
355 MmioWrite32 ( mI2CBaseAddress + R_IC_SS_SCL_HCNT, (UINT16)0x214 );
356 MmioWrite32 ( mI2CBaseAddress + R_IC_SS_SCL_LCNT, (UINT16)0x272 );
361 MmioWrite32 ( mI2CBaseAddress + R_IC_FS_SCL_HCNT, (UINT16)0x50 );
362 MmioWrite32 ( mI2CBaseAddress + R_IC_FS_SCL_LCNT, (UINT16)0xAD );
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/ |
| Smmu.c | 234 MmioWrite32 (Base, Value);
281 MmioWrite32 (Base + SMMU_RINT_GFSR, Value);
284 MmioWrite32 (Base + SMMU_CFG_GFIM, 0xFFFFFFFF);
288 MmioWrite32 (Base + SMMU_CFG_CBF, Value);
292 MmioWrite32 (Base + SMMU_RINT_CB_FSR(Index), FSR_FAULT);
312 MmioWrite32 ((UINTN)Table + SMMU_CB_S1CTBAR(Index), 0);
313 MmioWrite32 ((UINTN)Table + SMMU_CB_S2CR(Index), S2CR_TYPE_BYPASS);
353 MmioWrite32 (Smmu->S2Cbt + SMMU_CB_S1CTBAR(SMMU_OS_VMID), (UINT32) RShiftU64 ((UINT64)S1, SMMU_S1CBT_SHIFT));
356 MmioWrite32 ((UINTN)S1 + SMMU_CB(0) + SMMU_S1_SCTLR, SCTLR_CACHE_WBRAWA);
358 MmioWrite32 ((UINTN)S1 + SMMU_CB(1) + SMMU_S1_SCTLR, SCTLR_CACHE_NGNRE);
[all...] |
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchAccess.h | 433 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
434 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
440 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
441 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
443 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
444 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff & AndData)); \
445 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
450 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
451 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
453 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI) (…)
[all...] |
| /device/linaro/bootloader/edk2/Omap35xxPkg/TimerDxe/ |
| Timer.c | 91 MmioWrite32 (TISR, TISR_CLEAR_ALL);
188 MmioWrite32 (TCLR, TCLR_ST_OFF);
197 MmioWrite32 (TLDR, LoadValue);
198 MmioWrite32 (TCRR, LoadValue);
201 MmioWrite32 (TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
204 MmioWrite32 (TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/PciEmulation/ |
| PciEmulation.c | 43 MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
48 MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
60 MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
|
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Spi/ |
| MvSpiDxe.c | 88 MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
104 MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg);
118 MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg);
131 MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg);
155 MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
179 MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
217 MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
224 MmioWrite32 (SpiRegBase + SPI_INT_CAUSE_REG, 0x0);
225 MmioWrite32 (SpiRegBase + SPI_DATA_OUT_REG, DataToSend);
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Flash/ |
| Flash.c | 122 MmioWrite32 (GPMC_SYSCONFIG, SMARTIDLEMODE);
125 MmioWrite32 (GPMC_IRQSTATUS, 0x0);
126 MmioWrite32 (GPMC_IRQENABLE, 0x0);
129 MmioWrite32 (GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE);
132 MmioWrite32 (GPMC_CONFIG, WRITEPROTECT_HIGH);
135 MmioWrite32 (GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16);
136 MmioWrite32 (GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME);
137 MmioWrite32 (GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME);
138 MmioWrite32 (GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME);
139 MmioWrite32 (GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME);
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyUsbDxe/ |
| HiKeyUsbDxe.c | 52 MmioWrite32 (0xf8001864, 1);
53 MmioWrite32 (0xf8001868, 1);
109 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN0, BIT4);
117 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS0, Data);
127 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL4, Value);
141 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5, Value);
155 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5, Data);
157 MmioWrite32 (PERI_CTRL_BASE + 0x018, 0x70533483); //EYE_PATTERN
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/ |
| PciRootBridgeIo.c | 644 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
645 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
646 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
647 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
648 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
649 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
650 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG0);
651 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
670 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
671 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1);
[all...] |
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL011Uart/ |
| PL011Uart.c | 215 MmioWrite32 (UartBase + UARTCR, 0);
218 MmioWrite32 (UartBase + UARTIBRD, Integer);
219 MmioWrite32 (UartBase + UARTFBRD, Fractional);
222 MmioWrite32 (UartBase + UARTLCR_H, LineControl);
225 MmioWrite32 (UartBase + UARTECR, 0);
228 MmioWrite32 (UartBase + UARTCR,
300 MmioWrite32 (UartBase + UARTCR, Bits);
|
| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/ |
| Isp1761UsbDxe.h | 22 #define WRITE_REG32(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, Val)
23 #define WRITE_REG16(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, (UINT32) Val)
24 #define WRITE_REG8(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, (UINT32) Val)
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/MmcHostDxe/ |
| MmcHostDxe.c | 354 MmioWrite32 (MMCHS_BLK, BLEN_512BYTES);
360 MmioWrite32 (MMCHS_STAT, 0xFFFFFFFF);
363 MmioWrite32 (MMCHS_ARG, Argument);
367 //MmioWrite32 (MMCHS_IE, CmdInterruptEnableVal);
370 MmioWrite32 (MMCHS_CMD, MmcCmd);
391 MmioWrite32 (MMCHS_STAT, CC);
430 MmioWrite32 (MMCHS_SYSCONFIG, SOFTRESET);
435 MmioWrite32 (MMCHS_SYSCTL, SRA);
449 MmioWrite32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF));
464 MmioWrite32 (MMCHS_IE, (BADA_EN | CERR_EN | DEB_EN | DCRC_EN | DTO_EN | CIE_EN |
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Block/DwUfsHcDxe/ |
| DwUfsHcDxe.c | 72 MmioWrite32 (RegBase + UFS_HC_IS_OFFSET, ~0);
73 MmioWrite32 (RegBase + UFS_HC_UCMD_ARG1_OFFSET, (Attr << 16) | Index);
74 MmioWrite32 (RegBase + UFS_HC_UCMD_ARG2_OFFSET, 0);
75 MmioWrite32 (RegBase + UFS_HC_UCMD_ARG3_OFFSET, Value);
76 MmioWrite32 (RegBase + UFS_HC_UIC_CMD_OFFSET, UFS_UIC_DME_SET);
83 MmioWrite32 (RegBase + UFS_HC_IS_OFFSET, UFS_HC_IS_UCCS);
106 MmioWrite32 (RegBase + UFS_HC_IS_OFFSET, ~0);
107 MmioWrite32 (RegBase + UFS_HC_UCMD_ARG1_OFFSET, (Attr << 16) | Index);
108 MmioWrite32 (RegBase + UFS_HC_UCMD_ARG2_OFFSET, 0);
109 MmioWrite32 (RegBase + UFS_HC_UCMD_ARG3_OFFSET, 0);
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/GicV3/ |
| ArmGicV3Dxe.c | 292 MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
308 MmioWrite32 (mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR, 0xffffffff);
311 MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDISR + Index / 8, 0xffffffff);
317 MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget | ARM_GICD_IROUTER_IRM);
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/ |
| NorFlashJuno.c | 47 MmioWrite32 (ARM_VE_SYS_FLASH, 1);
|
| /device/linaro/bootloader/edk2/SecurityPkg/Library/Tpm2DeviceLibDTpm/ |
| Tpm2Ptp.c | 124 MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
192 MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
223 MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressHigh, (UINT32)RShiftU64 ((UINTN)CrbReg->CrbDataBuffer, 32));
224 MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressLow, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
225 MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof(CrbReg->CrbDataBuffer));
228 MmioWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof(CrbReg->CrbDataBuffer));
235 MmioWrite32((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);
304 MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
|
| /device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/ |
| ArmGicLib.c | 115 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);
203 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);
212 MmioWrite32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * RegOffset), 1 << RegShift);
238 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);
246 MmioWrite32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + (4 * RegOffset), 1 << RegShift);
293 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0);
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/ |
| InitController.c | 35 MmioWrite32 (AhciBaseAddr + EFI_AHCI_PORT_IS, EFI_AHCI_PORT_IS_CLEAR);
73 MmioWrite32 (AhciBaseAddr + EFI_AHCI_PI_OFFSET, (1 << PortCount) - 1);
93 MmioWrite32(AhciBaseAddr + PortRegAddr, RegVal);
|
| /device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/GicV2/ |
| ArmGicV2Dxe.c | 297 MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
302 MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCBPR, 0x7);
305 MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0xff);
|
| /device/linaro/bootloader/edk2/ArmPkg/Drivers/GenericWatchdogDxe/ |
| GenericWatchdogDxe.c | 51 return MmioWrite32 (GENERIC_WDOG_OFFSET_REG, Value);
67 return MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_ENABLED);
75 return MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_DISABLED);
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ |
| ArmVExpressSysConfig.c | 80 MmioWrite32(ARM_VE_SYS_CFGDATA_REG, *Data);
86 MmioWrite32(ARM_VE_SYS_CFGCTRL_REG, SysCfgCtrl);
232 MmioWrite32 ((ARM_VE_SCC_BASE + (Device * 4)),Value);
|
