| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 441 unsigned PredReg = MI->getOperand(5).getReg();
454 .addReg(PredReg)
647 unsigned PredReg = 0;
648 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) {
752 unsigned PredReg = 0;
753 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
848 unsigned PredReg = 0;
849 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
[all...] |
| ARMBaseInstrInfo.h | 454 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
476 ARMCC::CondCodes Pred, unsigned PredReg,
483 ARMCC::CondCodes Pred, unsigned PredReg,
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| MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg();
298 MIB.addImm(Pred).addReg(PredReg);
310 MIB.addImm(Pred).addReg(PredReg);
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| ARMBaseRegisterInfo.h | 173 unsigned PredReg = 0,
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| ARMBaseRegisterInfo.cpp | 414 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
425 .addImm(0).addImm(Pred).addReg(PredReg)
764 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
772 Offset, Pred, PredReg, TII);
776 Offset, Pred, PredReg, TII);
|
| ARMFrameLowering.cpp | 126 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
129 Pred, PredReg, TII, MIFlags);
132 Pred, PredReg, TII, MIFlags);
140 unsigned PredReg = 0) {
142 MIFlags, Pred, PredReg);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 172 unsigned PredReg = 0;
173 ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg);
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| ARMBaseRegisterInfo.h | 174 unsigned PredReg = 0,
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| Thumb2SizeReduction.cpp | 533 unsigned PredReg = 0;
534 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
614 unsigned PredReg = 0;
615 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
705 unsigned PredReg = 0;
706 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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| Thumb1RegisterInfo.cpp | 69 ARMCC::CondCodes Pred, unsigned PredReg,
79 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
412 unsigned PredReg;
413 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
|
| ARMExpandPseudoInsts.cpp | 647 unsigned PredReg = 0;
648 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 206 unsigned PredReg = 0;
207 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
|
| Thumb2SizeReduction.cpp | 471 unsigned PredReg = MI->getOperand(5).getReg();
484 .addReg(PredReg)
679 unsigned PredReg = 0;
680 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) {
782 unsigned PredReg = 0;
783 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
875 unsigned PredReg = 0;
876 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
[all...] |
| MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg();
298 MIB.addImm(Pred).addReg(PredReg);
310 MIB.addImm(Pred).addReg(PredReg);
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| ARMBaseRegisterInfo.h | 188 unsigned PredReg = 0,
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| ARMBaseRegisterInfo.cpp | 438 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
450 .add(predOps(Pred, PredReg))
783 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
791 Offset, Pred, PredReg, TII);
795 Offset, Pred, PredReg, TII);
[all...] |
| ARMFrameLowering.cpp | 171 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
174 Pred, PredReg, TII, MIFlags);
177 Pred, PredReg, TII, MIFlags);
185 unsigned PredReg = 0) {
187 MIFlags, Pred, PredReg);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCChecker.cpp | 68 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
72 PredReg = R;
77 NewPreds.insert(PredReg);
90 unsigned PredReg = Hexagon::NoRegister;
96 initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue);
98 initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue);
126 Defs[R].insert(PredSense(PredReg, isTrue));
178 Defs[*SRI].insert(PredSense(PredReg, isTrue));
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.h | 367 bool predCanBeUsedAsDotNew(const MachineInstr *MI, unsigned PredReg) const;
405 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
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| HexagonGenPredicate.cpp | 95 bool isScalarPred(Register PredReg);
302 bool HexagonGenPredicate::isScalarPred(Register PredReg) {
304 WorkQ.push(PredReg);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonGenPredicate.cpp | 118 bool isScalarPred(Register PredReg);
320 bool HexagonGenPredicate::isScalarPred(Register PredReg) {
322 WorkQ.push(PredReg);
|
| HexagonInstrInfo.h | 434 bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
467 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCChecker.h | 91 /// PredReg = predicate register, 0 if use/def not predicated,
92 /// Cond = true/false for if(PredReg)/if(!PredReg) respectively,
98 unsigned PredReg;
102 NewSense NS = { /*PredReg=*/ 0, /*IsFloat=*/ false, /*IsNVJ=*/ isNVJ,
107 NewSense NS = { /*PredReg=*/ PR, /*IsFloat=*/ false, /*IsNVJ=*/ false,
112 NewSense NS = { /*PredReg=*/ PR, /*IsFloat=*/ Float, /*IsNVJ=*/ false,
|
| HexagonMCDuplexInfo.cpp | 178 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
472 PredReg = MCI.getOperand(1).getReg(); // P0
474 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) {
[all...] |
