/external/llvm/lib/CodeGen/SelectionDAG/ |
DAGCombiner.cpp | 729 // Return true if this node is a setcc, or is a select_cc 731 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to 736 if (N.getOpcode() == ISD::SETCC) { 758 /// Return true if this is a SetCC-equivalent operation with only one use. [all...] |
TargetLowering.cpp | 149 /// SELECT_CC, and SETCC handlers. 155 && "Unsupported setcc type!"); 248 default: llvm_unreachable("Do not know how to soften this setcc!"); 265 ISD::SETCC, dl, 271 ISD::SETCC, dl, [all...] |
LegalizeDAG.cpp | 55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 56 /// will attempt merge setcc and brc instructions into brcc's. [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
DAGCombiner.cpp | 495 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 496 // that selects between the values 1 and 0, making it equivalent to a setcc. 502 if (N.getOpcode() == ISD::SETCC) { 521 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only [all...] |
LegalizeFloatTypes.cpp | 591 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break; 611 /// shared among BR_CC, SELECT_CC, and SETCC handlers. 618 assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!"); 675 default: assert(false && "Do not know how to soften this setcc!"); 686 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), 689 NewLHS = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), NewLHS, [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
SPUISelLowering.cpp | 313 setOperationAction(ISD::SETCC, MVT::i8, Legal); 314 setOperationAction(ISD::SETCC, MVT::i16, Legal); 315 setOperationAction(ISD::SETCC, MVT::i32, Legal); 316 setOperationAction(ISD::SETCC, MVT::i64, Legal); 317 setOperationAction(ISD::SETCC, MVT::f64, Custom); 502 // Return the Cell SPU's SETCC result type 506 // i8, i16 and i32 are valid SETCC result types [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
AVRISelLowering.cpp | 105 setOperationAction(ISD::SETCC, MVT::i8, Custom); 106 setOperationAction(ISD::SETCC, MVT::i16, Custom); 107 setOperationAction(ISD::SETCC, MVT::i32, Custom); 108 setOperationAction(ISD::SETCC, MVT::i64, Custom); 266 assert(!VT.isVector() && "No AVR SetCC type for vectors!"); 693 case ISD::SETCC: [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
TargetLowering.cpp | 154 /// SELECT_CC, and SETCC handlers. 160 && "Unsupported setcc type!"); 253 default: llvm_unreachable("Do not know how to soften this setcc!"); 270 ISD::SETCC, dl, 276 ISD::SETCC, dl, 756 case ISD::SETCC: { 760 // If (1) we only need the sign-bit, (2) the setcc operands are the same 761 // width as the setcc result, and (3) the result of a setcc conforms to 0 or 762 // -1, we may be able to bypass the setcc [all...] |
LegalizeVectorOps.cpp | 353 case ISD::SETCC: 729 case ISD::SETCC: [all...] |
DAGCombiner.cpp | [all...] |
LegalizeDAG.cpp | 83 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 84 /// will attempt merge setcc and brc instructions into brcc's. [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | 82 // X86 is weird. It always uses i8 for shift amounts and setcc results. 390 setOperationAction(ISD::SETCC, VT, Custom); 396 setOperationAction(ISD::SETCC, VT, Custom); 681 setOperationAction(ISD::SETCC, VT, Expand); [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEISelLowering.cpp | 79 setTargetDAGCombine(ISD::SETCC); 175 setOperationAction(ISD::SETCC, MVT::i32, Legal); 179 setOperationAction(ISD::SETCC, MVT::f32, Legal); 184 setOperationAction(ISD::SETCC, MVT::f64, Legal); 222 setOperationAction(ISD::SETCC, MVT::i64, Legal); 285 setOperationAction(ISD::SETCC, Ty, Legal); 322 setOperationAction(ISD::SETCC, Ty, Legal); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
MipsSEISelLowering.cpp | 105 setTargetDAGCombine(ISD::SETCC); 128 setOperationAction(ISD::SETCC, MVT::f16, Promote); 242 setOperationAction(ISD::SETCC, MVT::i32, Legal); 246 setOperationAction(ISD::SETCC, MVT::f32, Legal); 251 setOperationAction(ISD::SETCC, MVT::f64, Legal); 289 setOperationAction(ISD::SETCC, MVT::i64, Legal); 356 setOperationAction(ISD::SETCC, Ty, Legal); 393 setOperationAction(ISD::SETCC, Ty, Legal); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 115 setOperationAction(ISD::SETCC, MVT::i8, Custom); 116 setOperationAction(ISD::SETCC, MVT::i16, Custom); 188 case ISD::SETCC: return LowerSETCC(Op, DAG); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
SparcISelLowering.cpp | 731 // Sparc has no select or setcc: expand to SELECT_CC. 735 setOperationAction(ISD::SETCC, MVT::i32, Expand); 736 setOperationAction(ISD::SETCC, MVT::f32, Expand); 737 setOperationAction(ISD::SETCC, MVT::f64, Expand); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
X86ISelLowering.h | 89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS 91 SETCC, 93 // Same as SETCC except it's materialized with a sbb and the value is all 97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. 590 /// getSetCCResultType - Return the value type to use for ISD::SETCC. [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
HexagonISelLoweringHVX.cpp | 157 setOperationAction(ISD::SETCC, T, Custom); 179 setOperationAction(ISD::SETCC, BoolW, Custom); [all...] |
HexagonISelLowering.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 89 setOperationAction(ISD::SETCC, MVT::i8, Custom); 90 setOperationAction(ISD::SETCC, MVT::i16, Custom); 337 case ISD::SETCC: return LowerSETCC(Op, DAG); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
R600ISelLowering.cpp | 143 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); 144 setOperationAction(ISD::SETCC, MVT::v2i32, Expand); 160 setOperationAction(ISD::SETCC, MVT::i32, Expand); 161 setOperationAction(ISD::SETCC, MVT::f32, Expand); [all...] |
SIISelLowering.cpp | 191 setOperationAction(ISD::SETCC, MVT::i1, Promote); 192 setOperationAction(ISD::SETCC, MVT::v2i1, Expand); 193 setOperationAction(ISD::SETCC, MVT::v4i1, Expand); 194 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 631 setTargetDAGCombine(ISD::SETCC); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | 63 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so 108 setOperationAction(ISD::SETCC, MVT::i32, Custom); 109 setOperationAction(ISD::SETCC, MVT::i64, Custom); 110 setOperationAction(ISD::SETCC, MVT::f32, Custom); 111 setOperationAction(ISD::SETCC, MVT::f64, Custom); 159 setOperationAction(ISD::SETCC, MVT::f128, Custom); 262 setOperationAction(ISD::SETCC, MVT::f16, Promote); 332 setOperationAction(ISD::SETCC, MVT::v4f16, Expand); 365 setOperationAction(ISD::SETCC, MVT::v8f16, Expand); 543 setOperationAction(ISD::SETCC, MVT::v1f64, Expand) [all...] |
/external/llvm/lib/Target/AMDGPU/ |
R600ISelLowering.cpp | 110 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); 111 setOperationAction(ISD::SETCC, MVT::v2i32, Expand); 122 setOperationAction(ISD::SETCC, MVT::i32, Expand); 123 setOperationAction(ISD::SETCC, MVT::f32, Expand); [all...] |