| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| LegalizeDAG.cpp | 45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
[all...] |
| LegalizeIntegerTypes.cpp | 69 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
518 // Get the SETCC result using the canonical SETCC type.
519 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
524 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
774 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 122 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
167 setOperationAction(ISD::SETCC, MVT::i32, Custom);
168 setOperationAction(ISD::SETCC, MVT::i64, Custom);
169 setOperationAction(ISD::SETCC, MVT::f16, Custom);
170 setOperationAction(ISD::SETCC, MVT::f32, Custom);
171 setOperationAction(ISD::SETCC, MVT::f64, Custom);
226 setOperationAction(ISD::SETCC, MVT::f128, Custom);
370 setOperationAction(ISD::SETCC, MVT::f16, Promote);
409 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
436 setOperationAction(ISD::SETCC, MVT::v8f16, Expand)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 229 // setcc operations results (slt, sgt, ...).
264 // Used by legalize types to correctly generate the setcc result.
265 // Without this, every float setcc comes with a AND/OR with the result,
268 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
280 setOperationAction(ISD::SETCC, MVT::f32, Custom);
281 setOperationAction(ISD::SETCC, MVT::f64, Custom);
542 // Creates and returns an FPCmp node from a setcc node.
543 // Returns Op if setcc is not a floating point comparison.
545 // must be a SETCC node
546 if (Op.getOpcode() != ISD::SETCC)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 307 // setcc operations results (slt, sgt, ...).
342 // Used by legalize types to correctly generate the setcc result.
343 // Without this, every float setcc comes with a AND/OR with the result,
346 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
358 setOperationAction(ISD::SETCC, MVT::f32, Custom);
359 setOperationAction(ISD::SETCC, MVT::f64, Custom);
637 // Creates and returns an FPCmp node from a setcc node.
638 // Returns Op if setcc is not a floating point comparison.
640 // must be a SETCC node
641 if (Op.getOpcode() != ISD::SETCC)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 213 case ISD::SETCC: return "setcc";
330 default: llvm_unreachable("Unknown setcc condition!");
|
| LegalizeIntegerTypes.cpp | 77 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
578 // Promote all the way up to the canonical SetCC type.
619 // Get the SETCC result using the canonical SETCC type.
620 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
625 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 70 setOperationAction(ISD::SETCC, MVT::i64, Expand);
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 93 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
95 SETCC,
100 // Same as SETCC except it's materialized with a sbb and the value is all
104 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
769 /// Return the value type to use for ISD::SETCC.
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 76 setOperationAction(ISD::SETCC, MVT::i16, Promote);
140 // SETCC always sets the CC register. Technically that is an i1 register, but
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsISelLowering.cpp | 90 // setcc operations results (slt, sgt, ...).
118 // Used by legalize types to correctly generate the setcc result.
119 // Without this, every float setcc comes with a AND/OR with the result,
122 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
221 setTargetDAGCombine(ISD::SETCC);
491 // Creates and returns an FPCmp node from a setcc node.
492 // Returns Op if setcc is not a floating point comparison.
494 // must be a SETCC node
495 if (Op.getOpcode() != ISD::SETCC)
651 case ISD::SETCC
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 543 else if (Cond.getOpcode() == ISD::SETCC)
|
| SelectionDAGDumper.cpp | 254 case ISD::SETCC: return "setcc";
359 default: llvm_unreachable("Unknown setcc condition!");
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 102 setOperationAction(ISD::SETCC, VT, Expand);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 110 // X86 is weird. It always uses i8 for shift amounts and setcc results.
423 setOperationAction(ISD::SETCC, VT, Custom);
429 setOperationAction(ISD::SETCC, VT, Custom);
713 setOperationAction(ISD::SETCC, VT, Expand);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 73 "Number of (sext(setcc)) nodes expanded into GPR sequence.");
75 "Number of (zext(setcc)) nodes expanded into GPR sequence.");
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| SelectionDAG.h | 562 /// getSetCC - Helper function to make it easier to build SetCC's if you just
571 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 60 // setcc operations results (slt, sgt, ...).
138 // Used by legalize types to correctly generate the setcc result.
139 // Without this, every float setcc comes with a AND/OR with the result,
142 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
362 // setcc r1, r2, r3
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 573 /// associated with the SetCC condition, and whether or not the field is
617 // We can codegen setcc op, imm very efficiently compared to a brcond.
619 // setcc op, 0
649 } else if (Imm == ~0U) { // setcc op, -1
819 case ISD::SETCC:
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 381 setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote);
382 setFP16OperationAction(ISD::SETCC, MVT::v2f16, Legal, Expand);
514 // setcc for f16x2 needs special handling to prevent legalizer's
517 setTargetDAGCombine(ISD::SETCC);
[all...] |
