| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/ |
| invalid-mips5.s | 37 dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
38 dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
39 dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips4/ |
| valid.s | 141 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
142 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
143 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
144 dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
145 dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips5/ |
| valid.s | 141 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
142 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
143 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
144 dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
145 dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64/ |
| valid.s | 148 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
149 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
150 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
151 dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
152 dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 163 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
164 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
165 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
166 dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
167 dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 157 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
158 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
159 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
160 dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
161 dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 157 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
158 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
159 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
160 dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
161 dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
[all...] |
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 106 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
107 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
108 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 115 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
116 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
117 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 115 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
116 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
117 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 115 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
116 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
117 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /bionic/libc/arch-mips/string/ |
| strcmp.S | 51 # define SRL dsrl
|
| strncmp.S | 53 # define SRL dsrl
|
| /art/runtime/arch/mips64/ |
| quick_entrypoints_mips64.S | 640 dsrl $t1, $t1, 4 # enforce 16 byte stack alignment
692 dsrl $v1, $v0, 32 # put high half of result in v1
733 dsrl $t1, $ra, 32
[all...] |
| /external/llvm/test/MC/Mips/micromips64r6/ |
| valid.s | 307 dsrl $1, $2, 2 # CHECK: dsrl $1, $2, 2 # encoding: [0x58,0x22,0x10,0x40]
|
| /external/v8/src/mips64/ |
| macro-assembler-mips64.cc | [all...] |
| assembler-mips64.h | [all...] |
| assembler-mips64.cc | 2175 void Assembler::dsrl(Register rd, Register rt, uint16_t sa) { function in class:v8::internal::Assembler
[all...] |
| /external/v8/src/regexp/mips64/ |
| regexp-macro-assembler-mips64.cc | 779 __ dsrl(a1, a1, 1);
[all...] |
| /external/v8/src/compiler/mips64/ |
| code-generator-mips64.cc | [all...] |
