/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
RegAllocBasic.cpp | 57 /// algorithm. It prioritizes live virtual registers by spill weight and spills 202 // Spill or split all live virtual registers currently unified under PhysReg 226 // Spill each interfering vreg allocated to PhysReg or an alias. 228 LiveInterval &Spill = *Intfs[i]; 231 if (!VRM->hasPhys(Spill.reg)) 236 Matrix->unassign(Spill); 238 // Spill the extracted interval. 239 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats); 240 spiller().spill(LRE); 259 // Populate a list of physical register spill candidates [all...] |
RegisterScavenging.cpp | 14 /// them to spill slots. 267 // Expire scavenge spill frameindex uses. 409 // we have to spill, and can only place the restore after From then 461 RegScavenger::spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj, 488 // trying to spill a smaller register, the large slot would be found 489 // first, thus making it impossible to spill the larger register later. 498 // We need to scavenge a register but have no spill slot, the target 507 // otherwise, use the emergency stack spill slot. 509 // Spill the scavenged register before \p Before. 512 std::string Msg = std::string("Error while trying to spill ") [all...] |
InlineSpiller.cpp | 77 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden, 78 cl::desc("Disable inline spill hoisting")); 111 /// siblings. To hoist a spill to another BB, we need to find out a live 112 /// sibling there and use it as the source of the new spill. 148 void addToMergeableSpills(MachineInstr &Spill, int StackSlot, 150 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot); 168 // Variables that are valid during spill(), but used by multiple methods. 174 // All registers to spill to StackSlot, including the main register. 204 void spill(LiveRangeEdit &) override; 247 // When spilling a virtual register, we also spill any snippets it is connecte 1075 void InlineSpiller::spill(LiveRangeEdit &edit) { function in class:InlineSpiller [all...] |
RegAllocPBQP.cpp | 14 // register assignment. If any variables are selected for spilling then spill 169 /// Spill the given VReg. 191 /// Set spill costs for each node in the PBQP reg-alloc graph. 197 // A minimum spill costs, so that register constraints can can be set 684 VRegSpiller.spill(LRE); 696 assert(!LI.empty() && "Empty spill range."); 732 // Spill VReg. If this introduces new intervals we'll need another round 785 // All intervals have a spill weight that is mostly proportional to the number 811 // * Spill if necessary [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
RegisterScavenging.h | 14 /// to spill slots. 46 /// Information on scavenged registers (held in a spill slot). 50 /// A spill slot used for scavenging a register post register allocation. 218 /// Spill a register after position \p After and reload it before position 220 ScavengedInfo &spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
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/external/bcc/src/lua/bpf/ |
bpf.lua | 20 -- * Variables with liveness analysis and other meta (spill information, compile-time value) 118 assert(vinfo.reg, 'attempt to spill VAR that doesn\'t have an allocated register') 119 vinfo.spill = (var + 1) * ffi.sizeof('uint64_t') -- Index by (variable number) * (register width) 120 emit(BPF.MEM + BPF.STX + BPF.DW, 10, vinfo.reg, -vinfo.spill, 0) 127 assert(vinfo.spill, 'attempt to fill register with a VAR that isn\'t spilled') 128 emit(BPF.MEM + BPF.LDX + BPF.DW, reg, 10, -vinfo.spill, 0) 130 vinfo.spill = nil 135 -- Specific register requested, must spill/move existing variable 137 for k,v in pairs(V) do -- Spill any variable that has this register 167 assert(reg, 'VAR '..var..'fill/spill failed' [all...] |
builtins.lua | 153 e.reg_spill(src) -- Spill to avoid overwriting 212 if e.V[dst].spill then 213 e.emit(BPF.ALU64 + BPF.ADD + BPF.K, 1, 0, 0, -e.V[dst].spill) 228 e.reg_spill(src) -- Spill to avoid overwriting 289 e.reg_alloc(e.tmpvar, 1) -- Spill anything in R1 (unnamed tmp variable) 313 e.reg_alloc(e.tmpvar, 1) -- Spill anything in R1 (unnamed tmp variable) 336 e.reg_alloc(e.tmpvar, 1) -- Spill anything in R1 (unnamed tmp variable) 341 e.reg_alloc(e.tmpvar, 3) -- Spill anything in R2 (unnamed tmp variable) 362 e.reg_alloc(e.tmpvar, 1) -- Spill 366 e.reg_alloc(e.tmpvar, 2) -- Spill [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
RegAllocBasic.cpp | 79 /// algorithm. It prioritizes live virtual registers by spill weight and spills 393 // Spill the extracted interval. 395 spiller().spill(LRE); 402 // Spill or split all live virtual registers currently unified under PhysReg 423 // Spill each interfering vreg allocated to PhysReg or an alias. 484 // Populate a list of physical register spill candidates. 506 // must have less spill weight. 511 // Try to spill another interfering reg with less spill weight. 518 "Interference after spill.") [all...] |
RenderMachineFunction.cpp | 973 const LiveInterval *spill = *siItr; local [all...] |
InlineSpiller.cpp | 49 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden, 50 cl::desc("Disable inline spill hoisting")); 67 // Variables that are valid during spill(), but used by multiple methods. 73 // All registers to spill to StackSlot, including the main register. 87 // True when all reaching defs were reloads: No spill is necessary. 96 // The preferred register to spill. 152 void spill(LiveRangeEdit &); 201 // When spilling a virtual register, we also spill any snippets it is connected 207 // spill slots which can be important in tight loops. 232 // %Reg = COPY %snip / SPILL %snip, fi 1251 void InlineSpiller::spill(LiveRangeEdit &edit) { function in class:InlineSpiller [all...] |
RegAllocLinearScan.cpp | 262 /// is available, or spill. 269 /// findIntervalsToSpill - Determine the intervals to spill for the 270 /// specified interval. It's passed the physical registers whose spill 539 // Rewrite spill code and update the PhysRegsUsed set. 612 // physical register or spill an interval (possibly this one) in order to 677 // register allocator had to spill other registers in its register class. 769 /// updateSpillWeights - updates the spill weights of the specifed physical 792 // e.g. allocating for GR32, bh is not used, updating bl spill weight. 793 // bl should get the same spill weight otherwise it will be chosen 794 // as a spill candidate since spilling bh doesn't make ebx available [all...] |
RegAllocGreedy.cpp | 55 SplitSpillMode("split-spill-mode", cl::Hidden, 56 cl::desc("Spill mode for splitting live ranges"), 160 float MaxWeight; ///< Maximum spill weight evicted. 546 // Never evict spill products. They cannot split or spill. 550 // register for it. This is indicated by an infinite spill weight. These 624 // hints, and only evict smaller spill weights. 692 // Number of spill code instructions to insert. 715 // Accumulate the total frequency of inserted spill code. 845 // Use the spill placer to determine the live bundles. GrowRegion pretend [all...] |
/art/compiler/utils/arm/ |
jni_macro_assembler_arm_vixl.cc | 123 for (const ManagedRegisterSpill& spill : entry_spills) { 124 ArmManagedRegister reg = spill.AsArm(); 127 offset += spill.getSize();
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/art/compiler/utils/arm64/ |
jni_macro_assembler_arm64.cc | 722 for (const ManagedRegisterSpill& spill : entry_spills) { 723 Arm64ManagedRegister reg = spill.AsArm64(); 726 offset += spill.getSize();
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/bionic/libc/arch-mips/bionic/ |
setjmp.S | 214 REG_S $ra, RAOFF($sp) # spill state 330 move $s1, $a1 # temp spill
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/external/llvm/lib/CodeGen/ |
InlineSpiller.cpp | 55 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden, 56 cl::desc("Disable inline spill hoisting")); 85 /// siblings. To hoist a spill to another BB, we need to find out a live 86 /// sibling there and use it as the source of the new spill. 123 void addToMergeableSpills(MachineInstr &Spill, int StackSlot, 125 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot); 144 // Variables that are valid during spill(), but used by multiple methods. 150 // All registers to spill to StackSlot, including the main register. 181 void spill(LiveRangeEdit &) override; 229 // When spilling a virtual register, we also spill any snippets it is connecte 1020 void InlineSpiller::spill(LiveRangeEdit &edit) { function in class:InlineSpiller [all...] |
RegAllocPBQP.cpp | 14 // register assignment. If any variables are selected for spilling then spill 138 /// \brief Spill the given VReg. 160 /// @brief Set spill costs for each node in the PBQP reg-alloc graph. 166 // A minimum spill costs, so that register constraints can can be set 643 VRegSpiller.spill(LRE); 655 assert(!LI.empty() && "Empty spill range."); 691 // Spill VReg. If this introduces new intervals we'll need another round 736 // All intervals have a spill weight that is mostly proportional to the number 762 // * Spill if necessary
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/external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
nv50_ir_ra.cpp | 322 void spill(Instruction *defi, Value *slot, LValue *); 810 SpillCodeInserter& spill; member in class:nv50_ir::GCRA 1144 GCRA::GCRA(Function *fn, SpillCodeInserter& spill) : 1147 spill(spill) 1618 SpillCodeInserter::spill(Instruction *defi, Value *slot, LValue *lval) function in class:nv50_ir::SpillCodeInserter [all...] |
/device/linaro/bootloader/edk2/AppPkg/Applications/Python/PyMod-2.7.2/Lib/ |
pydoc.py | 737 def spill(msg, attrs, predicate):
function in function:.docclass 1158 def spill(msg, attrs, predicate): function in function:TextDoc.docclass [all...] |
/device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.10/PyMod-2.7.10/Lib/ |
pydoc.py | 788 def spill(msg, attrs, predicate):
function in function:.docclass 1221 def spill(msg, attrs, predicate): function in function:TextDoc.docclass [all...] |
/device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Lib/ |
pydoc.py | 737 def spill(msg, attrs, predicate):
function in function:.docclass 1158 def spill(msg, attrs, predicate): function in function:TextDoc.docclass [all...] |
/external/python/cpython2/Lib/ |
pydoc.py | 776 def spill(msg, attrs, predicate): function in function:.docclass 1209 def spill(msg, attrs, predicate): function in function:TextDoc.docclass [all...] |
/external/python/cpython3/Lib/ |
pydoc.py | 801 def spill(msg, attrs, predicate): function in function:.docclass 1266 def spill(msg, attrs, predicate): function in function:TextDoc.docclass [all...] |
/art/compiler/utils/x86_64/ |
assembler_x86_64_test.cc | [all...] |
/device/linaro/bootloader/edk2/EmulatorPkg/Unix/Host/X64/ |
Gasket.S | 6 # Callee allocates 32 bytes on stack to spill registers 24 // This is the 32 (0x20) byte to spill registers and 8 bytes to align stack on 16 byte boundry. 28 // 32 byte shadow to spill rcx-r9, 8 bytes to align stack on 16 byte boundry [all...] |