| /external/mesa3d/src/intel/compiler/ |
| brw_vec4_cse.cpp | 130 a->dst.writemask == b->dst.writemask &&
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| brw_vec4_tes.cpp | 227 dst.writemask = brw_writemask_for_size(instr->num_components);
255 dst.writemask = brw_writemask_for_size(instr->num_components);
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| brw_shader.h | 81 using brw_reg::writemask;
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| test_vec4_copy_propagation.cpp | 164 v->emit(v->MOV(writemask(a, WRITEMASK_XYZ), brw_imm_f(1.0f)));
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| brw_vec4_builder.h | 352 writemask(vgrf(BRW_REGISTER_TYPE_UD), WRITEMASK_X);
605 inst->dst.writemask != WRITEMASK_XYZW) {
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| /external/virglrenderer/src/gallium/include/pipe/ |
| p_state.h | 225 unsigned writemask:1; /**< allow depth buffer writes? */ member in struct:pipe_depth_state
238 unsigned writemask:8; member in struct:pipe_stencil_state
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_text.c | 443 uint *writemask )
451 *writemask = TGSI_WRITEMASK_NONE;
455 *writemask |= TGSI_WRITEMASK_X;
459 *writemask |= TGSI_WRITEMASK_Y;
463 *writemask |= TGSI_WRITEMASK_Z;
467 *writemask |= TGSI_WRITEMASK_W;
470 if (*writemask == TGSI_WRITEMASK_NONE) {
471 report_error( ctx, "Writemask expected" );
478 *writemask = TGSI_WRITEMASK_XYZW;
812 uint writemask; local
1289 uint writemask; local
[all...] |
| tgsi_scan.h | 185 ubyte writemask; member in struct:tgsi_array_info
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| tgsi_dump.c | 225 uint writemask )
227 if (writemask != TGSI_WRITEMASK_XYZW) {
229 if (writemask & TGSI_WRITEMASK_X)
231 if (writemask & TGSI_WRITEMASK_Y)
233 if (writemask & TGSI_WRITEMASK_Z)
235 if (writemask & TGSI_WRITEMASK_W)
599 _dump_writemask( ctx, dst->Register.WriteMask );
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| tgsi_transform.h | 228 unsigned file, unsigned index, unsigned writemask)
232 reg->Register.WriteMask = writemask;
284 inst.Dst[0].Register.WriteMask = dst_writemask;
311 inst.Dst[0].Register.WriteMask = dst_writemask;
341 inst.Dst[0].Register.WriteMask = dst_writemask;
369 inst.Dst[0].Register.WriteMask = dst_writemask;
414 inst.Dst[0].Register.WriteMask = dst_writemask;
468 inst.Dst[0].Register.WriteMask = dst_writemask;
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| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| tgsi_text.c | 430 uint *writemask )
438 *writemask = TGSI_WRITEMASK_NONE;
442 *writemask |= TGSI_WRITEMASK_X;
446 *writemask |= TGSI_WRITEMASK_Y;
450 *writemask |= TGSI_WRITEMASK_Z;
454 *writemask |= TGSI_WRITEMASK_W;
457 if (*writemask == TGSI_WRITEMASK_NONE) {
458 report_error( ctx, "Writemask expected" );
465 *writemask = TGSI_WRITEMASK_XYZW;
799 uint writemask; local
1264 uint writemask; local
[all...] |
| tgsi_dump.c | 221 uint writemask )
223 if (writemask != TGSI_WRITEMASK_XYZW) {
225 if (writemask & TGSI_WRITEMASK_X)
227 if (writemask & TGSI_WRITEMASK_Y)
229 if (writemask & TGSI_WRITEMASK_Z)
231 if (writemask & TGSI_WRITEMASK_W)
558 _dump_writemask( ctx, dst->Register.WriteMask );
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| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_pipe_blend.c | 118 perRT[i].renderTargetWriteMask = bs->rt[i].writemask;
324 blend->rt[i].writemask = templ->rt[i].colormask;
327 blend->rt[i].writemask = templ->rt[0].colormask;
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| svga_tgsi_emit.h | 267 * Apply a writemask to the given SVGA3dShaderDestToken, returning a
271 writemask(SVGA3dShaderDestToken dest, unsigned mask)
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| /external/mesa3d/src/compiler/glsl/ |
| ir_builder.cpp | 49 assign(deref lhs, operand rhs, operand condition, int writemask)
56 writemask);
68 assign(deref lhs, operand rhs, int writemask)
70 return assign(lhs, rhs, (ir_rvalue *) NULL, writemask);
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| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_simple_shaders.c | 226 * IMM {0,0,0,1} // (if writemask != 0xf)
227 * MOV TEMP[0], IMM[0] // (if writemask != 0xf)
228 * TEX TEMP[0].writemask, IN[0], SAMP[0], 2D;
235 * \param writemask mask of TGSI_WRITEMASK_x
241 unsigned writemask,
275 if (writemask != TGSI_WRITEMASK_XYZW) {
283 ureg_writemask(temp, writemask),
286 ureg_load_tex(ureg, ureg_writemask(temp, writemask), tex, sampler,
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| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_state.c | 469 int writemask = depth_stencil->stencil[0].writemask & 0xff; local
475 STENCIL_WRITE_MASK(writemask));
498 int wmask = depth_stencil->stencil[1].writemask & 0xff;
534 if (depth_stencil->depth.writemask)
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/nv30/ |
| nv30_state.c | 224 SB_DATA (so, cso->depth.writemask);
237 SB_DATA (so, cso->stencil[0].writemask);
253 SB_DATA (so, cso->stencil[1].writemask);
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| /external/mesa3d/src/mesa/state_tracker/ |
| st_cb_clear.c | 251 depth_stencil.depth.writemask = 1;
264 depth_stencil.stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff;
375 return (ctx->Stencil.WriteMask[0] & stencilMax) == 0;
388 return (ctx->Stencil.WriteMask[0] & stencilMax) != stencilMax;
464 * This can only happen when the stencil writemask is not a full mask.
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| /external/mesa3d/src/compiler/nir/ |
| nir_builder.h | 561 unsigned writemask)
568 nir_intrinsic_set_write_mask(store, writemask);
576 nir_ssa_def *value, unsigned writemask)
584 store->const_index[0] = writemask & ((1 << num_components) - 1);
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_aos.c | 268 * Writemask
271 if (reg->Register.WriteMask != TGSI_WRITEMASK_XYZW) {
272 LLVMValueRef writemask; local
274 writemask = lp_build_const_mask_aos_swizzled(bld->bld_base.base.gallivm,
276 reg->Register.WriteMask,
281 mask = LLVMBuildAnd(builder, mask, writemask, "");
283 mask = writemask;
445 * assume a full writemask and then let LLVM optimization passes eliminate
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| /external/mesa3d/src/gallium/drivers/softpipe/ |
| sp_quad_depth_test.c | 433 * \param wrtMask writemask controlling which bits are changed in the
517 /* apply bit-wise stencil buffer writemask */
599 /* Update our internal copy only if writemask set. Even if
600 * depth.writemask is FALSE, may still need to write out buffer
603 if (softpipe->depth_stencil->depth.writemask) {
645 wrtMask = softpipe->depth_stencil->stencil[face].writemask;
834 if (qs->softpipe->depth_stencil->depth.writemask)
915 boolean depthwrite = qs->softpipe->depth_stencil->depth.writemask;
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| /external/virglrenderer/tests/ |
| test_virgl_cmd.c | 61 dsa.depth.writemask = 1;
384 dsa.depth.writemask = 1;
648 dsa.depth.writemask = 1;
893 dsa.depth.writemask = 1;
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_shader_tgsi_mem.c | 398 uint writemask = inst->Dst[0].Register.WriteMask; local
399 uint count = util_last_bit(writemask);
449 unsigned writemask = inst->Dst[0].Register.WriteMask; local
456 if (!(writemask & (1 << chan))) {
662 unsigned writemask = inst->Dst[0].Register.WriteMask; local
664 while (writemask) {
671 u_bit_scan_consecutive_range(&writemask, &start, &count)
731 unsigned writemask = inst->Dst[0].Register.WriteMask; local
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_compiler.c | 170 * writemask is honoured.
172 void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask)
184 inst->U.I.DstReg.WriteMask &= writemask;
255 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W;
266 inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ;
281 inst_mad->U.I.DstReg.WriteMask = RC_MASK_XYZ;
335 inst_add->U.I.DstReg.WriteMask = RC_MASK_X;
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