1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_EXYNOS_DRM_H_ 20 #define _UAPI_EXYNOS_DRM_H_ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 struct drm_exynos_gem_create { 26 __u64 size; 27 __u32 flags; 28 __u32 handle; 29 }; 30 struct drm_exynos_gem_map { 31 __u32 handle; 32 __u32 reserved; 33 __u64 offset; 34 }; 35 struct drm_exynos_gem_info { 36 __u32 handle; 37 __u32 flags; 38 __u64 size; 39 }; 40 struct drm_exynos_vidi_connection { 41 __u32 connection; 42 __u32 extensions; 43 __u64 edid; 44 }; 45 enum e_drm_exynos_gem_mem_type { 46 EXYNOS_BO_CONTIG = 0 << 0, 47 EXYNOS_BO_NONCONTIG = 1 << 0, 48 EXYNOS_BO_NONCACHABLE = 0 << 1, 49 EXYNOS_BO_CACHABLE = 1 << 1, 50 EXYNOS_BO_WC = 1 << 2, 51 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | EXYNOS_BO_WC 52 }; 53 struct drm_exynos_g2d_get_ver { 54 __u32 major; 55 __u32 minor; 56 }; 57 struct drm_exynos_g2d_cmd { 58 __u32 offset; 59 __u32 data; 60 }; 61 enum drm_exynos_g2d_buf_type { 62 G2D_BUF_USERPTR = 1 << 31, 63 }; 64 enum drm_exynos_g2d_event_type { 65 G2D_EVENT_NOT, 66 G2D_EVENT_NONSTOP, 67 G2D_EVENT_STOP, 68 }; 69 struct drm_exynos_g2d_userptr { 70 unsigned long userptr; 71 unsigned long size; 72 }; 73 struct drm_exynos_g2d_set_cmdlist { 74 __u64 cmd; 75 __u64 cmd_buf; 76 __u32 cmd_nr; 77 __u32 cmd_buf_nr; 78 __u64 event_type; 79 __u64 user_data; 80 }; 81 struct drm_exynos_g2d_exec { 82 __u64 async; 83 }; 84 struct drm_exynos_ioctl_ipp_get_res { 85 __u32 count_ipps; 86 __u32 reserved; 87 __u64 ipp_id_ptr; 88 }; 89 enum drm_exynos_ipp_format_type { 90 DRM_EXYNOS_IPP_FORMAT_SOURCE = 0x01, 91 DRM_EXYNOS_IPP_FORMAT_DESTINATION = 0x02, 92 }; 93 struct drm_exynos_ipp_format { 94 __u32 fourcc; 95 __u32 type; 96 __u64 modifier; 97 }; 98 enum drm_exynos_ipp_capability { 99 DRM_EXYNOS_IPP_CAP_CROP = 0x01, 100 DRM_EXYNOS_IPP_CAP_ROTATE = 0x02, 101 DRM_EXYNOS_IPP_CAP_SCALE = 0x04, 102 DRM_EXYNOS_IPP_CAP_CONVERT = 0x08, 103 }; 104 struct drm_exynos_ioctl_ipp_get_caps { 105 __u32 ipp_id; 106 __u32 capabilities; 107 __u32 reserved; 108 __u32 formats_count; 109 __u64 formats_ptr; 110 }; 111 enum drm_exynos_ipp_limit_type { 112 DRM_EXYNOS_IPP_LIMIT_TYPE_SIZE = 0x0001, 113 DRM_EXYNOS_IPP_LIMIT_TYPE_SCALE = 0x0002, 114 DRM_EXYNOS_IPP_LIMIT_SIZE_BUFFER = 0x0001 << 16, 115 DRM_EXYNOS_IPP_LIMIT_SIZE_AREA = 0x0002 << 16, 116 DRM_EXYNOS_IPP_LIMIT_SIZE_ROTATED = 0x0003 << 16, 117 DRM_EXYNOS_IPP_LIMIT_TYPE_MASK = 0x000f, 118 DRM_EXYNOS_IPP_LIMIT_SIZE_MASK = 0x000f << 16, 119 }; 120 struct drm_exynos_ipp_limit_val { 121 __u32 min; 122 __u32 max; 123 __u32 align; 124 __u32 reserved; 125 }; 126 struct drm_exynos_ipp_limit { 127 __u32 type; 128 __u32 reserved; 129 struct drm_exynos_ipp_limit_val h; 130 struct drm_exynos_ipp_limit_val v; 131 }; 132 struct drm_exynos_ioctl_ipp_get_limits { 133 __u32 ipp_id; 134 __u32 fourcc; 135 __u64 modifier; 136 __u32 type; 137 __u32 limits_count; 138 __u64 limits_ptr; 139 }; 140 enum drm_exynos_ipp_task_id { 141 DRM_EXYNOS_IPP_TASK_BUFFER = 0x0001, 142 DRM_EXYNOS_IPP_TASK_RECTANGLE = 0x0002, 143 DRM_EXYNOS_IPP_TASK_TRANSFORM = 0x0003, 144 DRM_EXYNOS_IPP_TASK_ALPHA = 0x0004, 145 DRM_EXYNOS_IPP_TASK_TYPE_SOURCE = 0x0001 << 16, 146 DRM_EXYNOS_IPP_TASK_TYPE_DESTINATION = 0x0002 << 16, 147 }; 148 struct drm_exynos_ipp_task_buffer { 149 __u32 id; 150 __u32 fourcc; 151 __u32 width, height; 152 __u32 gem_id[4]; 153 __u32 offset[4]; 154 __u32 pitch[4]; 155 __u64 modifier; 156 }; 157 struct drm_exynos_ipp_task_rect { 158 __u32 id; 159 __u32 reserved; 160 __u32 x; 161 __u32 y; 162 __u32 w; 163 __u32 h; 164 }; 165 struct drm_exynos_ipp_task_transform { 166 __u32 id; 167 __u32 rotation; 168 }; 169 struct drm_exynos_ipp_task_alpha { 170 __u32 id; 171 __u32 value; 172 }; 173 enum drm_exynos_ipp_flag { 174 DRM_EXYNOS_IPP_FLAG_EVENT = 0x01, 175 DRM_EXYNOS_IPP_FLAG_TEST_ONLY = 0x02, 176 DRM_EXYNOS_IPP_FLAG_NONBLOCK = 0x04, 177 }; 178 #define DRM_EXYNOS_IPP_FLAGS (DRM_EXYNOS_IPP_FLAG_EVENT | DRM_EXYNOS_IPP_FLAG_TEST_ONLY | DRM_EXYNOS_IPP_FLAG_NONBLOCK) 179 struct drm_exynos_ioctl_ipp_commit { 180 __u32 ipp_id; 181 __u32 flags; 182 __u32 reserved; 183 __u32 params_size; 184 __u64 params_ptr; 185 __u64 user_data; 186 }; 187 #define DRM_EXYNOS_GEM_CREATE 0x00 188 #define DRM_EXYNOS_GEM_MAP 0x01 189 #define DRM_EXYNOS_GEM_GET 0x04 190 #define DRM_EXYNOS_VIDI_CONNECTION 0x07 191 #define DRM_EXYNOS_G2D_GET_VER 0x20 192 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 193 #define DRM_EXYNOS_G2D_EXEC 0x22 194 #define DRM_EXYNOS_IPP_GET_RESOURCES 0x40 195 #define DRM_EXYNOS_IPP_GET_CAPS 0x41 196 #define DRM_EXYNOS_IPP_GET_LIMITS 0x42 197 #define DRM_EXYNOS_IPP_COMMIT 0x43 198 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) 199 #define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map) 200 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) 201 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) 202 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) 203 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) 204 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) 205 #define DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_RESOURCES, struct drm_exynos_ioctl_ipp_get_res) 206 #define DRM_IOCTL_EXYNOS_IPP_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_CAPS, struct drm_exynos_ioctl_ipp_get_caps) 207 #define DRM_IOCTL_EXYNOS_IPP_GET_LIMITS DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_LIMITS, struct drm_exynos_ioctl_ipp_get_limits) 208 #define DRM_IOCTL_EXYNOS_IPP_COMMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_COMMIT, struct drm_exynos_ioctl_ipp_commit) 209 #define DRM_EXYNOS_G2D_EVENT 0x80000000 210 #define DRM_EXYNOS_IPP_EVENT 0x80000002 211 struct drm_exynos_g2d_event { 212 struct drm_event base; 213 __u64 user_data; 214 __u32 tv_sec; 215 __u32 tv_usec; 216 __u32 cmdlist_no; 217 __u32 reserved; 218 }; 219 struct drm_exynos_ipp_event { 220 struct drm_event base; 221 __u64 user_data; 222 __u32 tv_sec; 223 __u32 tv_usec; 224 __u32 ipp_id; 225 __u32 sequence; 226 __u64 reserved; 227 }; 228 #ifdef __cplusplus 229 } 230 #endif 231 #endif 232
