1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __VMWGFX_DRM_H__ 20 #define __VMWGFX_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define DRM_VMW_MAX_SURFACE_FACES 6 26 #define DRM_VMW_MAX_MIP_LEVELS 24 27 #define DRM_VMW_GET_PARAM 0 28 #define DRM_VMW_ALLOC_DMABUF 1 29 #define DRM_VMW_ALLOC_BO 1 30 #define DRM_VMW_UNREF_DMABUF 2 31 #define DRM_VMW_HANDLE_CLOSE 2 32 #define DRM_VMW_CURSOR_BYPASS 3 33 #define DRM_VMW_CONTROL_STREAM 4 34 #define DRM_VMW_CLAIM_STREAM 5 35 #define DRM_VMW_UNREF_STREAM 6 36 #define DRM_VMW_CREATE_CONTEXT 7 37 #define DRM_VMW_UNREF_CONTEXT 8 38 #define DRM_VMW_CREATE_SURFACE 9 39 #define DRM_VMW_UNREF_SURFACE 10 40 #define DRM_VMW_REF_SURFACE 11 41 #define DRM_VMW_EXECBUF 12 42 #define DRM_VMW_GET_3D_CAP 13 43 #define DRM_VMW_FENCE_WAIT 14 44 #define DRM_VMW_FENCE_SIGNALED 15 45 #define DRM_VMW_FENCE_UNREF 16 46 #define DRM_VMW_FENCE_EVENT 17 47 #define DRM_VMW_PRESENT 18 48 #define DRM_VMW_PRESENT_READBACK 19 49 #define DRM_VMW_UPDATE_LAYOUT 20 50 #define DRM_VMW_CREATE_SHADER 21 51 #define DRM_VMW_UNREF_SHADER 22 52 #define DRM_VMW_GB_SURFACE_CREATE 23 53 #define DRM_VMW_GB_SURFACE_REF 24 54 #define DRM_VMW_SYNCCPU 25 55 #define DRM_VMW_CREATE_EXTENDED_CONTEXT 26 56 #define DRM_VMW_GB_SURFACE_CREATE_EXT 27 57 #define DRM_VMW_GB_SURFACE_REF_EXT 28 58 #define DRM_VMW_PARAM_NUM_STREAMS 0 59 #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 60 #define DRM_VMW_PARAM_3D 2 61 #define DRM_VMW_PARAM_HW_CAPS 3 62 #define DRM_VMW_PARAM_FIFO_CAPS 4 63 #define DRM_VMW_PARAM_MAX_FB_SIZE 5 64 #define DRM_VMW_PARAM_FIFO_HW_VERSION 6 65 #define DRM_VMW_PARAM_MAX_SURF_MEMORY 7 66 #define DRM_VMW_PARAM_3D_CAPS_SIZE 8 67 #define DRM_VMW_PARAM_MAX_MOB_MEMORY 9 68 #define DRM_VMW_PARAM_MAX_MOB_SIZE 10 69 #define DRM_VMW_PARAM_SCREEN_TARGET 11 70 #define DRM_VMW_PARAM_DX 12 71 #define DRM_VMW_PARAM_HW_CAPS2 13 72 #define DRM_VMW_PARAM_SM4_1 14 73 enum drm_vmw_handle_type { 74 DRM_VMW_HANDLE_LEGACY = 0, 75 DRM_VMW_HANDLE_PRIME = 1 76 }; 77 struct drm_vmw_getparam_arg { 78 __u64 value; 79 __u32 param; 80 __u32 pad64; 81 }; 82 struct drm_vmw_context_arg { 83 __s32 cid; 84 __u32 pad64; 85 }; 86 struct drm_vmw_surface_create_req { 87 __u32 flags; 88 __u32 format; 89 __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES]; 90 __u64 size_addr; 91 __s32 shareable; 92 __s32 scanout; 93 }; 94 struct drm_vmw_surface_arg { 95 __s32 sid; 96 enum drm_vmw_handle_type handle_type; 97 }; 98 struct drm_vmw_size { 99 __u32 width; 100 __u32 height; 101 __u32 depth; 102 __u32 pad64; 103 }; 104 union drm_vmw_surface_create_arg { 105 struct drm_vmw_surface_arg rep; 106 struct drm_vmw_surface_create_req req; 107 }; 108 union drm_vmw_surface_reference_arg { 109 struct drm_vmw_surface_create_req rep; 110 struct drm_vmw_surface_arg req; 111 }; 112 #define DRM_VMW_EXECBUF_VERSION 2 113 #define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0) 114 #define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1) 115 struct drm_vmw_execbuf_arg { 116 __u64 commands; 117 __u32 command_size; 118 __u32 throttle_us; 119 __u64 fence_rep; 120 __u32 version; 121 __u32 flags; 122 __u32 context_handle; 123 __s32 imported_fence_fd; 124 }; 125 struct drm_vmw_fence_rep { 126 __u32 handle; 127 __u32 mask; 128 __u32 seqno; 129 __u32 passed_seqno; 130 __s32 fd; 131 __s32 error; 132 }; 133 struct drm_vmw_alloc_bo_req { 134 __u32 size; 135 __u32 pad64; 136 }; 137 #define drm_vmw_alloc_dmabuf_req drm_vmw_alloc_bo_req 138 struct drm_vmw_bo_rep { 139 __u64 map_handle; 140 __u32 handle; 141 __u32 cur_gmr_id; 142 __u32 cur_gmr_offset; 143 __u32 pad64; 144 }; 145 #define drm_vmw_dmabuf_rep drm_vmw_bo_rep 146 union drm_vmw_alloc_bo_arg { 147 struct drm_vmw_alloc_bo_req req; 148 struct drm_vmw_bo_rep rep; 149 }; 150 #define drm_vmw_alloc_dmabuf_arg drm_vmw_alloc_bo_arg 151 struct drm_vmw_rect { 152 __s32 x; 153 __s32 y; 154 __u32 w; 155 __u32 h; 156 }; 157 struct drm_vmw_control_stream_arg { 158 __u32 stream_id; 159 __u32 enabled; 160 __u32 flags; 161 __u32 color_key; 162 __u32 handle; 163 __u32 offset; 164 __s32 format; 165 __u32 size; 166 __u32 width; 167 __u32 height; 168 __u32 pitch[3]; 169 __u32 pad64; 170 struct drm_vmw_rect src; 171 struct drm_vmw_rect dst; 172 }; 173 #define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0) 174 #define DRM_VMW_CURSOR_BYPASS_FLAGS (1) 175 struct drm_vmw_cursor_bypass_arg { 176 __u32 flags; 177 __u32 crtc_id; 178 __s32 xpos; 179 __s32 ypos; 180 __s32 xhot; 181 __s32 yhot; 182 }; 183 struct drm_vmw_stream_arg { 184 __u32 stream_id; 185 __u32 pad64; 186 }; 187 struct drm_vmw_get_3d_cap_arg { 188 __u64 buffer; 189 __u32 max_size; 190 __u32 pad64; 191 }; 192 #define DRM_VMW_FENCE_FLAG_EXEC (1 << 0) 193 #define DRM_VMW_FENCE_FLAG_QUERY (1 << 1) 194 #define DRM_VMW_WAIT_OPTION_UNREF (1 << 0) 195 struct drm_vmw_fence_wait_arg { 196 __u32 handle; 197 __s32 cookie_valid; 198 __u64 kernel_cookie; 199 __u64 timeout_us; 200 __s32 lazy; 201 __s32 flags; 202 __s32 wait_options; 203 __s32 pad64; 204 }; 205 struct drm_vmw_fence_signaled_arg { 206 __u32 handle; 207 __u32 flags; 208 __s32 signaled; 209 __u32 passed_seqno; 210 __u32 signaled_flags; 211 __u32 pad64; 212 }; 213 struct drm_vmw_fence_arg { 214 __u32 handle; 215 __u32 pad64; 216 }; 217 #define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000 218 struct drm_vmw_event_fence { 219 struct drm_event base; 220 __u64 user_data; 221 __u32 tv_sec; 222 __u32 tv_usec; 223 }; 224 #define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0) 225 struct drm_vmw_fence_event_arg { 226 __u64 fence_rep; 227 __u64 user_data; 228 __u32 handle; 229 __u32 flags; 230 }; 231 struct drm_vmw_present_arg { 232 __u32 fb_id; 233 __u32 sid; 234 __s32 dest_x; 235 __s32 dest_y; 236 __u64 clips_ptr; 237 __u32 num_clips; 238 __u32 pad64; 239 }; 240 struct drm_vmw_present_readback_arg { 241 __u32 fb_id; 242 __u32 num_clips; 243 __u64 clips_ptr; 244 __u64 fence_rep; 245 }; 246 struct drm_vmw_update_layout_arg { 247 __u32 num_outputs; 248 __u32 pad64; 249 __u64 rects; 250 }; 251 enum drm_vmw_shader_type { 252 drm_vmw_shader_type_vs = 0, 253 drm_vmw_shader_type_ps, 254 }; 255 struct drm_vmw_shader_create_arg { 256 enum drm_vmw_shader_type shader_type; 257 __u32 size; 258 __u32 buffer_handle; 259 __u32 shader_handle; 260 __u64 offset; 261 }; 262 struct drm_vmw_shader_arg { 263 __u32 handle; 264 __u32 pad64; 265 }; 266 enum drm_vmw_surface_flags { 267 drm_vmw_surface_flag_shareable = (1 << 0), 268 drm_vmw_surface_flag_scanout = (1 << 1), 269 drm_vmw_surface_flag_create_buffer = (1 << 2) 270 }; 271 struct drm_vmw_gb_surface_create_req { 272 __u32 svga3d_flags; 273 __u32 format; 274 __u32 mip_levels; 275 enum drm_vmw_surface_flags drm_surface_flags; 276 __u32 multisample_count; 277 __u32 autogen_filter; 278 __u32 buffer_handle; 279 __u32 array_size; 280 struct drm_vmw_size base_size; 281 }; 282 struct drm_vmw_gb_surface_create_rep { 283 __u32 handle; 284 __u32 backup_size; 285 __u32 buffer_handle; 286 __u32 buffer_size; 287 __u64 buffer_map_handle; 288 }; 289 union drm_vmw_gb_surface_create_arg { 290 struct drm_vmw_gb_surface_create_rep rep; 291 struct drm_vmw_gb_surface_create_req req; 292 }; 293 struct drm_vmw_gb_surface_ref_rep { 294 struct drm_vmw_gb_surface_create_req creq; 295 struct drm_vmw_gb_surface_create_rep crep; 296 }; 297 union drm_vmw_gb_surface_reference_arg { 298 struct drm_vmw_gb_surface_ref_rep rep; 299 struct drm_vmw_surface_arg req; 300 }; 301 enum drm_vmw_synccpu_flags { 302 drm_vmw_synccpu_read = (1 << 0), 303 drm_vmw_synccpu_write = (1 << 1), 304 drm_vmw_synccpu_dontblock = (1 << 2), 305 drm_vmw_synccpu_allow_cs = (1 << 3) 306 }; 307 enum drm_vmw_synccpu_op { 308 drm_vmw_synccpu_grab, 309 drm_vmw_synccpu_release 310 }; 311 struct drm_vmw_synccpu_arg { 312 enum drm_vmw_synccpu_op op; 313 enum drm_vmw_synccpu_flags flags; 314 __u32 handle; 315 __u32 pad64; 316 }; 317 enum drm_vmw_extended_context { 318 drm_vmw_context_legacy, 319 drm_vmw_context_dx 320 }; 321 union drm_vmw_extended_context_arg { 322 enum drm_vmw_extended_context req; 323 struct drm_vmw_context_arg rep; 324 }; 325 struct drm_vmw_handle_close_arg { 326 __u32 handle; 327 __u32 pad64; 328 }; 329 #define drm_vmw_unref_dmabuf_arg drm_vmw_handle_close_arg 330 enum drm_vmw_surface_version { 331 drm_vmw_gb_surface_v1 332 }; 333 struct drm_vmw_gb_surface_create_ext_req { 334 struct drm_vmw_gb_surface_create_req base; 335 enum drm_vmw_surface_version version; 336 uint32_t svga3d_flags_upper_32_bits; 337 SVGA3dMSPattern multisample_pattern; 338 SVGA3dMSQualityLevel quality_level; 339 uint64_t must_be_zero; 340 }; 341 union drm_vmw_gb_surface_create_ext_arg { 342 struct drm_vmw_gb_surface_create_rep rep; 343 struct drm_vmw_gb_surface_create_ext_req req; 344 }; 345 struct drm_vmw_gb_surface_ref_ext_rep { 346 struct drm_vmw_gb_surface_create_ext_req creq; 347 struct drm_vmw_gb_surface_create_rep crep; 348 }; 349 union drm_vmw_gb_surface_reference_ext_arg { 350 struct drm_vmw_gb_surface_ref_ext_rep rep; 351 struct drm_vmw_surface_arg req; 352 }; 353 #ifdef __cplusplus 354 } 355 #endif 356 #endif 357
