1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __ETNAVIV_DRM_H__ 20 #define __ETNAVIV_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 struct drm_etnaviv_timespec { 26 __s64 tv_sec; 27 __s64 tv_nsec; 28 }; 29 #define ETNAVIV_PARAM_GPU_MODEL 0x01 30 #define ETNAVIV_PARAM_GPU_REVISION 0x02 31 #define ETNAVIV_PARAM_GPU_FEATURES_0 0x03 32 #define ETNAVIV_PARAM_GPU_FEATURES_1 0x04 33 #define ETNAVIV_PARAM_GPU_FEATURES_2 0x05 34 #define ETNAVIV_PARAM_GPU_FEATURES_3 0x06 35 #define ETNAVIV_PARAM_GPU_FEATURES_4 0x07 36 #define ETNAVIV_PARAM_GPU_FEATURES_5 0x08 37 #define ETNAVIV_PARAM_GPU_FEATURES_6 0x09 38 #define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a 39 #define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b 40 #define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c 41 #define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d 42 #define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e 43 #define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f 44 #define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10 45 #define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11 46 #define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12 47 #define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13 48 #define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14 49 #define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15 50 #define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16 51 #define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17 52 #define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18 53 #define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19 54 #define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a 55 #define ETNA_MAX_PIPES 4 56 struct drm_etnaviv_param { 57 __u32 pipe; 58 __u32 param; 59 __u64 value; 60 }; 61 #define ETNA_BO_CACHE_MASK 0x000f0000 62 #define ETNA_BO_CACHED 0x00010000 63 #define ETNA_BO_WC 0x00020000 64 #define ETNA_BO_UNCACHED 0x00040000 65 #define ETNA_BO_FORCE_MMU 0x00100000 66 struct drm_etnaviv_gem_new { 67 __u64 size; 68 __u32 flags; 69 __u32 handle; 70 }; 71 struct drm_etnaviv_gem_info { 72 __u32 handle; 73 __u32 pad; 74 __u64 offset; 75 }; 76 #define ETNA_PREP_READ 0x01 77 #define ETNA_PREP_WRITE 0x02 78 #define ETNA_PREP_NOSYNC 0x04 79 struct drm_etnaviv_gem_cpu_prep { 80 __u32 handle; 81 __u32 op; 82 struct drm_etnaviv_timespec timeout; 83 }; 84 struct drm_etnaviv_gem_cpu_fini { 85 __u32 handle; 86 __u32 flags; 87 }; 88 struct drm_etnaviv_gem_submit_reloc { 89 __u32 submit_offset; 90 __u32 reloc_idx; 91 __u64 reloc_offset; 92 __u32 flags; 93 }; 94 #define ETNA_SUBMIT_BO_READ 0x0001 95 #define ETNA_SUBMIT_BO_WRITE 0x0002 96 struct drm_etnaviv_gem_submit_bo { 97 __u32 flags; 98 __u32 handle; 99 __u64 presumed; 100 }; 101 #define ETNA_PM_PROCESS_PRE 0x0001 102 #define ETNA_PM_PROCESS_POST 0x0002 103 struct drm_etnaviv_gem_submit_pmr { 104 __u32 flags; 105 __u8 domain; 106 __u8 pad; 107 __u16 signal; 108 __u32 sequence; 109 __u32 read_offset; 110 __u32 read_idx; 111 }; 112 #define ETNA_SUBMIT_NO_IMPLICIT 0x0001 113 #define ETNA_SUBMIT_FENCE_FD_IN 0x0002 114 #define ETNA_SUBMIT_FENCE_FD_OUT 0x0004 115 #define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | ETNA_SUBMIT_FENCE_FD_IN | ETNA_SUBMIT_FENCE_FD_OUT) 116 #define ETNA_PIPE_3D 0x00 117 #define ETNA_PIPE_2D 0x01 118 #define ETNA_PIPE_VG 0x02 119 struct drm_etnaviv_gem_submit { 120 __u32 fence; 121 __u32 pipe; 122 __u32 exec_state; 123 __u32 nr_bos; 124 __u32 nr_relocs; 125 __u32 stream_size; 126 __u64 bos; 127 __u64 relocs; 128 __u64 stream; 129 __u32 flags; 130 __s32 fence_fd; 131 __u64 pmrs; 132 __u32 nr_pmrs; 133 __u32 pad; 134 }; 135 #define ETNA_WAIT_NONBLOCK 0x01 136 struct drm_etnaviv_wait_fence { 137 __u32 pipe; 138 __u32 fence; 139 __u32 flags; 140 __u32 pad; 141 struct drm_etnaviv_timespec timeout; 142 }; 143 #define ETNA_USERPTR_READ 0x01 144 #define ETNA_USERPTR_WRITE 0x02 145 struct drm_etnaviv_gem_userptr { 146 __u64 user_ptr; 147 __u64 user_size; 148 __u32 flags; 149 __u32 handle; 150 }; 151 struct drm_etnaviv_gem_wait { 152 __u32 pipe; 153 __u32 handle; 154 __u32 flags; 155 __u32 pad; 156 struct drm_etnaviv_timespec timeout; 157 }; 158 struct drm_etnaviv_pm_domain { 159 __u32 pipe; 160 __u8 iter; 161 __u8 id; 162 __u16 nr_signals; 163 char name[64]; 164 }; 165 struct drm_etnaviv_pm_signal { 166 __u32 pipe; 167 __u8 domain; 168 __u8 pad; 169 __u16 iter; 170 __u16 id; 171 char name[64]; 172 }; 173 #define DRM_ETNAVIV_GET_PARAM 0x00 174 #define DRM_ETNAVIV_GEM_NEW 0x02 175 #define DRM_ETNAVIV_GEM_INFO 0x03 176 #define DRM_ETNAVIV_GEM_CPU_PREP 0x04 177 #define DRM_ETNAVIV_GEM_CPU_FINI 0x05 178 #define DRM_ETNAVIV_GEM_SUBMIT 0x06 179 #define DRM_ETNAVIV_WAIT_FENCE 0x07 180 #define DRM_ETNAVIV_GEM_USERPTR 0x08 181 #define DRM_ETNAVIV_GEM_WAIT 0x09 182 #define DRM_ETNAVIV_PM_QUERY_DOM 0x0a 183 #define DRM_ETNAVIV_PM_QUERY_SIG 0x0b 184 #define DRM_ETNAVIV_NUM_IOCTLS 0x0c 185 #define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param) 186 #define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new) 187 #define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info) 188 #define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep) 189 #define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini) 190 #define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit) 191 #define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence) 192 #define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr) 193 #define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait) 194 #define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain) 195 #define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal) 196 #ifdef __cplusplus 197 } 198 #endif 199 #endif 200
