1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_VC4_DRM_H_ 20 #define _UAPI_VC4_DRM_H_ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define DRM_VC4_SUBMIT_CL 0x00 26 #define DRM_VC4_WAIT_SEQNO 0x01 27 #define DRM_VC4_WAIT_BO 0x02 28 #define DRM_VC4_CREATE_BO 0x03 29 #define DRM_VC4_MMAP_BO 0x04 30 #define DRM_VC4_CREATE_SHADER_BO 0x05 31 #define DRM_VC4_GET_HANG_STATE 0x06 32 #define DRM_VC4_GET_PARAM 0x07 33 #define DRM_VC4_SET_TILING 0x08 34 #define DRM_VC4_GET_TILING 0x09 35 #define DRM_VC4_LABEL_BO 0x0a 36 #define DRM_VC4_GEM_MADVISE 0x0b 37 #define DRM_VC4_PERFMON_CREATE 0x0c 38 #define DRM_VC4_PERFMON_DESTROY 0x0d 39 #define DRM_VC4_PERFMON_GET_VALUES 0x0e 40 #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) 41 #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) 42 #define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) 43 #define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) 44 #define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) 45 #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) 46 #define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) 47 #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) 48 #define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) 49 #define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) 50 #define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) 51 #define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise) 52 #define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create) 53 #define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy) 54 #define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values) 55 struct drm_vc4_submit_rcl_surface { 56 __u32 hindex; 57 __u32 offset; 58 __u16 bits; 59 #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) 60 __u16 flags; 61 }; 62 struct drm_vc4_submit_cl { 63 __u64 bin_cl; 64 __u64 shader_rec; 65 __u64 uniforms; 66 __u64 bo_handles; 67 __u32 bin_cl_size; 68 __u32 shader_rec_size; 69 __u32 shader_rec_count; 70 __u32 uniforms_size; 71 __u32 bo_handle_count; 72 __u16 width; 73 __u16 height; 74 __u8 min_x_tile; 75 __u8 min_y_tile; 76 __u8 max_x_tile; 77 __u8 max_y_tile; 78 struct drm_vc4_submit_rcl_surface color_read; 79 struct drm_vc4_submit_rcl_surface color_write; 80 struct drm_vc4_submit_rcl_surface zs_read; 81 struct drm_vc4_submit_rcl_surface zs_write; 82 struct drm_vc4_submit_rcl_surface msaa_color_write; 83 struct drm_vc4_submit_rcl_surface msaa_zs_write; 84 __u32 clear_color[2]; 85 __u32 clear_z; 86 __u8 clear_s; 87 __u32 pad : 24; 88 #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) 89 #define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1) 90 #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2) 91 #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3) 92 __u32 flags; 93 __u64 seqno; 94 __u32 perfmonid; 95 __u32 in_sync; 96 __u32 out_sync; 97 __u32 pad2; 98 }; 99 struct drm_vc4_wait_seqno { 100 __u64 seqno; 101 __u64 timeout_ns; 102 }; 103 struct drm_vc4_wait_bo { 104 __u32 handle; 105 __u32 pad; 106 __u64 timeout_ns; 107 }; 108 struct drm_vc4_create_bo { 109 __u32 size; 110 __u32 flags; 111 __u32 handle; 112 __u32 pad; 113 }; 114 struct drm_vc4_mmap_bo { 115 __u32 handle; 116 __u32 flags; 117 __u64 offset; 118 }; 119 struct drm_vc4_create_shader_bo { 120 __u32 size; 121 __u32 flags; 122 __u64 data; 123 __u32 handle; 124 __u32 pad; 125 }; 126 struct drm_vc4_get_hang_state_bo { 127 __u32 handle; 128 __u32 paddr; 129 __u32 size; 130 __u32 pad; 131 }; 132 struct drm_vc4_get_hang_state { 133 __u64 bo; 134 __u32 bo_count; 135 __u32 start_bin, start_render; 136 __u32 ct0ca, ct0ea; 137 __u32 ct1ca, ct1ea; 138 __u32 ct0cs, ct1cs; 139 __u32 ct0ra0, ct1ra0; 140 __u32 bpca, bpcs; 141 __u32 bpoa, bpos; 142 __u32 vpmbase; 143 __u32 dbge; 144 __u32 fdbgo; 145 __u32 fdbgb; 146 __u32 fdbgr; 147 __u32 fdbgs; 148 __u32 errstat; 149 __u32 pad[16]; 150 }; 151 #define DRM_VC4_PARAM_V3D_IDENT0 0 152 #define DRM_VC4_PARAM_V3D_IDENT1 1 153 #define DRM_VC4_PARAM_V3D_IDENT2 2 154 #define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 155 #define DRM_VC4_PARAM_SUPPORTS_ETC1 4 156 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 157 #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6 158 #define DRM_VC4_PARAM_SUPPORTS_MADVISE 7 159 #define DRM_VC4_PARAM_SUPPORTS_PERFMON 8 160 struct drm_vc4_get_param { 161 __u32 param; 162 __u32 pad; 163 __u64 value; 164 }; 165 struct drm_vc4_get_tiling { 166 __u32 handle; 167 __u32 flags; 168 __u64 modifier; 169 }; 170 struct drm_vc4_set_tiling { 171 __u32 handle; 172 __u32 flags; 173 __u64 modifier; 174 }; 175 struct drm_vc4_label_bo { 176 __u32 handle; 177 __u32 len; 178 __u64 name; 179 }; 180 #define VC4_MADV_WILLNEED 0 181 #define VC4_MADV_DONTNEED 1 182 #define __VC4_MADV_PURGED 2 183 #define __VC4_MADV_NOTSUPP 3 184 struct drm_vc4_gem_madvise { 185 __u32 handle; 186 __u32 madv; 187 __u32 retained; 188 __u32 pad; 189 }; 190 enum { 191 VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER, 192 VC4_PERFCNT_FEP_VALID_PRIMS_RENDER, 193 VC4_PERFCNT_FEP_CLIPPED_QUADS, 194 VC4_PERFCNT_FEP_VALID_QUADS, 195 VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL, 196 VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL, 197 VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL, 198 VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE, 199 VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE, 200 VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF, 201 VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT, 202 VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING, 203 VC4_PERFCNT_PSE_PRIMS_REVERSED, 204 VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES, 205 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING, 206 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING, 207 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST, 208 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS, 209 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD, 210 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS, 211 VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT, 212 VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS, 213 VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT, 214 VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS, 215 VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED, 216 VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS, 217 VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED, 218 VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED, 219 VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT, 220 VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS, 221 VC4_PERFCNT_NUM_EVENTS, 222 }; 223 #define DRM_VC4_MAX_PERF_COUNTERS 16 224 struct drm_vc4_perfmon_create { 225 __u32 id; 226 __u32 ncounters; 227 __u8 events[DRM_VC4_MAX_PERF_COUNTERS]; 228 }; 229 struct drm_vc4_perfmon_destroy { 230 __u32 id; 231 }; 232 struct drm_vc4_perfmon_get_values { 233 __u32 id; 234 __u64 values_ptr; 235 }; 236 #ifdef __cplusplus 237 } 238 #endif 239 #endif 240
