1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _VIA_DRM_H_ 20 #define _VIA_DRM_H_ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #ifndef _VIA_DEFINES_ 26 #define _VIA_DEFINES_ 27 #define VIA_NR_SAREA_CLIPRECTS 8 28 #define VIA_NR_XVMC_PORTS 10 29 #define VIA_NR_XVMC_LOCKS 5 30 #define VIA_MAX_CACHELINE_SIZE 64 31 #define XVMCLOCKPTR(saPriv,lockNo) ((volatile struct drm_hw_lock *) (((((unsigned long) (saPriv)->XvMCLockArea) + (VIA_MAX_CACHELINE_SIZE - 1)) & ~(VIA_MAX_CACHELINE_SIZE - 1)) + VIA_MAX_CACHELINE_SIZE * (lockNo))) 32 #define VIA_NR_TEX_REGIONS 64 33 #define VIA_LOG_MIN_TEX_REGION_SIZE 16 34 #endif 35 #define VIA_UPLOAD_TEX0IMAGE 0x1 36 #define VIA_UPLOAD_TEX1IMAGE 0x2 37 #define VIA_UPLOAD_CTX 0x4 38 #define VIA_UPLOAD_BUFFERS 0x8 39 #define VIA_UPLOAD_TEX0 0x10 40 #define VIA_UPLOAD_TEX1 0x20 41 #define VIA_UPLOAD_CLIPRECTS 0x40 42 #define VIA_UPLOAD_ALL 0xff 43 #define DRM_VIA_ALLOCMEM 0x00 44 #define DRM_VIA_FREEMEM 0x01 45 #define DRM_VIA_AGP_INIT 0x02 46 #define DRM_VIA_FB_INIT 0x03 47 #define DRM_VIA_MAP_INIT 0x04 48 #define DRM_VIA_DEC_FUTEX 0x05 49 #define NOT_USED 50 #define DRM_VIA_DMA_INIT 0x07 51 #define DRM_VIA_CMDBUFFER 0x08 52 #define DRM_VIA_FLUSH 0x09 53 #define DRM_VIA_PCICMD 0x0a 54 #define DRM_VIA_CMDBUF_SIZE 0x0b 55 #define NOT_USED 56 #define DRM_VIA_WAIT_IRQ 0x0d 57 #define DRM_VIA_DMA_BLIT 0x0e 58 #define DRM_VIA_BLIT_SYNC 0x0f 59 #define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t) 60 #define DRM_IOCTL_VIA_FREEMEM DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t) 61 #define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t) 62 #define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t) 63 #define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t) 64 #define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t) 65 #define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t) 66 #define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t) 67 #define DRM_IOCTL_VIA_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_VIA_FLUSH) 68 #define DRM_IOCTL_VIA_PCICMD DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t) 69 #define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, drm_via_cmdbuf_size_t) 70 #define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t) 71 #define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t) 72 #define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t) 73 #define VIA_TEX_SETUP_SIZE 8 74 #define VIA_FRONT 0x1 75 #define VIA_BACK 0x2 76 #define VIA_DEPTH 0x4 77 #define VIA_STENCIL 0x8 78 #define VIA_MEM_VIDEO 0 79 #define VIA_MEM_AGP 1 80 #define VIA_MEM_SYSTEM 2 81 #define VIA_MEM_MIXED 3 82 #define VIA_MEM_UNKNOWN 4 83 typedef struct { 84 __u32 offset; 85 __u32 size; 86 } drm_via_agp_t; 87 typedef struct { 88 __u32 offset; 89 __u32 size; 90 } drm_via_fb_t; 91 typedef struct { 92 __u32 context; 93 __u32 type; 94 __u32 size; 95 unsigned long index; 96 unsigned long offset; 97 } drm_via_mem_t; 98 typedef struct _drm_via_init { 99 enum { 100 VIA_INIT_MAP = 0x01, 101 VIA_CLEANUP_MAP = 0x02 102 } func; 103 unsigned long sarea_priv_offset; 104 unsigned long fb_offset; 105 unsigned long mmio_offset; 106 unsigned long agpAddr; 107 } drm_via_init_t; 108 typedef struct _drm_via_futex { 109 enum { 110 VIA_FUTEX_WAIT = 0x00, 111 VIA_FUTEX_WAKE = 0X01 112 } func; 113 __u32 ms; 114 __u32 lock; 115 __u32 val; 116 } drm_via_futex_t; 117 typedef struct _drm_via_dma_init { 118 enum { 119 VIA_INIT_DMA = 0x01, 120 VIA_CLEANUP_DMA = 0x02, 121 VIA_DMA_INITIALIZED = 0x03 122 } func; 123 unsigned long offset; 124 unsigned long size; 125 unsigned long reg_pause_addr; 126 } drm_via_dma_init_t; 127 typedef struct _drm_via_cmdbuffer { 128 char __user * buf; 129 unsigned long size; 130 } drm_via_cmdbuffer_t; 131 typedef struct _drm_via_tex_region { 132 unsigned char next, prev; 133 unsigned char inUse; 134 int age; 135 } drm_via_tex_region_t; 136 typedef struct _drm_via_sarea { 137 unsigned int dirty; 138 unsigned int nbox; 139 struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS]; 140 drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1]; 141 int texAge; 142 int ctxOwner; 143 int vertexPrim; 144 char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)]; 145 unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS]; 146 unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS]; 147 unsigned int XvMCCtxNoGrabbed; 148 unsigned int pfCurrentOffset; 149 } drm_via_sarea_t; 150 typedef struct _drm_via_cmdbuf_size { 151 enum { 152 VIA_CMDBUF_SPACE = 0x01, 153 VIA_CMDBUF_LAG = 0x02 154 } func; 155 int wait; 156 __u32 size; 157 } drm_via_cmdbuf_size_t; 158 typedef enum { 159 VIA_IRQ_ABSOLUTE = 0x0, 160 VIA_IRQ_RELATIVE = 0x1, 161 VIA_IRQ_SIGNAL = 0x10000000, 162 VIA_IRQ_FORCE_SEQUENCE = 0x20000000 163 } via_irq_seq_type_t; 164 #define VIA_IRQ_FLAGS_MASK 0xF0000000 165 enum drm_via_irqs { 166 drm_via_irq_hqv0 = 0, 167 drm_via_irq_hqv1, 168 drm_via_irq_dma0_dd, 169 drm_via_irq_dma0_td, 170 drm_via_irq_dma1_dd, 171 drm_via_irq_dma1_td, 172 drm_via_irq_num 173 }; 174 struct drm_via_wait_irq_request { 175 unsigned irq; 176 via_irq_seq_type_t type; 177 __u32 sequence; 178 __u32 signal; 179 }; 180 typedef union drm_via_irqwait { 181 struct drm_via_wait_irq_request request; 182 struct drm_wait_vblank_reply reply; 183 } drm_via_irqwait_t; 184 typedef struct drm_via_blitsync { 185 __u32 sync_handle; 186 unsigned engine; 187 } drm_via_blitsync_t; 188 typedef struct drm_via_dmablit { 189 __u32 num_lines; 190 __u32 line_length; 191 __u32 fb_addr; 192 __u32 fb_stride; 193 unsigned char * mem_addr; 194 __u32 mem_stride; 195 __u32 flags; 196 int to_fb; 197 drm_via_blitsync_t sync; 198 } drm_via_dmablit_t; 199 #ifdef __cplusplus 200 } 201 #endif 202 #endif 203
