1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef KFD_IOCTL_H_INCLUDED 20 #define KFD_IOCTL_H_INCLUDED 21 #include <drm/drm.h> 22 #include <linux/ioctl.h> 23 #define KFD_IOCTL_MAJOR_VERSION 1 24 #define KFD_IOCTL_MINOR_VERSION 1 25 struct kfd_ioctl_get_version_args { 26 __u32 major_version; 27 __u32 minor_version; 28 }; 29 #define KFD_IOC_QUEUE_TYPE_COMPUTE 0 30 #define KFD_IOC_QUEUE_TYPE_SDMA 1 31 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 2 32 #define KFD_MAX_QUEUE_PERCENTAGE 100 33 #define KFD_MAX_QUEUE_PRIORITY 15 34 struct kfd_ioctl_create_queue_args { 35 __u64 ring_base_address; 36 __u64 write_pointer_address; 37 __u64 read_pointer_address; 38 __u64 doorbell_offset; 39 __u32 ring_size; 40 __u32 gpu_id; 41 __u32 queue_type; 42 __u32 queue_percentage; 43 __u32 queue_priority; 44 __u32 queue_id; 45 __u64 eop_buffer_address; 46 __u64 eop_buffer_size; 47 __u64 ctx_save_restore_address; 48 __u32 ctx_save_restore_size; 49 __u32 ctl_stack_size; 50 }; 51 struct kfd_ioctl_destroy_queue_args { 52 __u32 queue_id; 53 __u32 pad; 54 }; 55 struct kfd_ioctl_update_queue_args { 56 __u64 ring_base_address; 57 __u32 queue_id; 58 __u32 ring_size; 59 __u32 queue_percentage; 60 __u32 queue_priority; 61 }; 62 struct kfd_ioctl_set_cu_mask_args { 63 __u32 queue_id; 64 __u32 num_cu_mask; 65 __u64 cu_mask_ptr; 66 }; 67 struct kfd_ioctl_get_queue_wave_state_args { 68 __u64 ctl_stack_address; 69 __u32 ctl_stack_used_size; 70 __u32 save_area_used_size; 71 __u32 queue_id; 72 __u32 pad; 73 }; 74 #define KFD_IOC_CACHE_POLICY_COHERENT 0 75 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 76 struct kfd_ioctl_set_memory_policy_args { 77 __u64 alternate_aperture_base; 78 __u64 alternate_aperture_size; 79 __u32 gpu_id; 80 __u32 default_policy; 81 __u32 alternate_policy; 82 __u32 pad; 83 }; 84 struct kfd_ioctl_get_clock_counters_args { 85 __u64 gpu_clock_counter; 86 __u64 cpu_clock_counter; 87 __u64 system_clock_counter; 88 __u64 system_clock_freq; 89 __u32 gpu_id; 90 __u32 pad; 91 }; 92 struct kfd_process_device_apertures { 93 __u64 lds_base; 94 __u64 lds_limit; 95 __u64 scratch_base; 96 __u64 scratch_limit; 97 __u64 gpuvm_base; 98 __u64 gpuvm_limit; 99 __u32 gpu_id; 100 __u32 pad; 101 }; 102 #define NUM_OF_SUPPORTED_GPUS 7 103 struct kfd_ioctl_get_process_apertures_args { 104 struct kfd_process_device_apertures process_apertures[NUM_OF_SUPPORTED_GPUS]; 105 __u32 num_of_nodes; 106 __u32 pad; 107 }; 108 struct kfd_ioctl_get_process_apertures_new_args { 109 __u64 kfd_process_device_apertures_ptr; 110 __u32 num_of_nodes; 111 __u32 pad; 112 }; 113 #define MAX_ALLOWED_NUM_POINTS 100 114 #define MAX_ALLOWED_AW_BUFF_SIZE 4096 115 #define MAX_ALLOWED_WAC_BUFF_SIZE 128 116 struct kfd_ioctl_dbg_register_args { 117 __u32 gpu_id; 118 __u32 pad; 119 }; 120 struct kfd_ioctl_dbg_unregister_args { 121 __u32 gpu_id; 122 __u32 pad; 123 }; 124 struct kfd_ioctl_dbg_address_watch_args { 125 __u64 content_ptr; 126 __u32 gpu_id; 127 __u32 buf_size_in_bytes; 128 }; 129 struct kfd_ioctl_dbg_wave_control_args { 130 __u64 content_ptr; 131 __u32 gpu_id; 132 __u32 buf_size_in_bytes; 133 }; 134 #define KFD_IOC_EVENT_SIGNAL 0 135 #define KFD_IOC_EVENT_NODECHANGE 1 136 #define KFD_IOC_EVENT_DEVICESTATECHANGE 2 137 #define KFD_IOC_EVENT_HW_EXCEPTION 3 138 #define KFD_IOC_EVENT_SYSTEM_EVENT 4 139 #define KFD_IOC_EVENT_DEBUG_EVENT 5 140 #define KFD_IOC_EVENT_PROFILE_EVENT 6 141 #define KFD_IOC_EVENT_QUEUE_EVENT 7 142 #define KFD_IOC_EVENT_MEMORY 8 143 #define KFD_IOC_WAIT_RESULT_COMPLETE 0 144 #define KFD_IOC_WAIT_RESULT_TIMEOUT 1 145 #define KFD_IOC_WAIT_RESULT_FAIL 2 146 #define KFD_SIGNAL_EVENT_LIMIT 4096 147 #define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0 148 #define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1 149 #define KFD_HW_EXCEPTION_GPU_HANG 0 150 #define KFD_HW_EXCEPTION_ECC 1 151 struct kfd_ioctl_create_event_args { 152 __u64 event_page_offset; 153 __u32 event_trigger_data; 154 __u32 event_type; 155 __u32 auto_reset; 156 __u32 node_id; 157 __u32 event_id; 158 __u32 event_slot_index; 159 }; 160 struct kfd_ioctl_destroy_event_args { 161 __u32 event_id; 162 __u32 pad; 163 }; 164 struct kfd_ioctl_set_event_args { 165 __u32 event_id; 166 __u32 pad; 167 }; 168 struct kfd_ioctl_reset_event_args { 169 __u32 event_id; 170 __u32 pad; 171 }; 172 struct kfd_memory_exception_failure { 173 __u32 NotPresent; 174 __u32 ReadOnly; 175 __u32 NoExecute; 176 __u32 imprecise; 177 }; 178 struct kfd_hsa_memory_exception_data { 179 struct kfd_memory_exception_failure failure; 180 __u64 va; 181 __u32 gpu_id; 182 __u32 pad; 183 }; 184 struct kfd_hsa_hw_exception_data { 185 __u32 reset_type; 186 __u32 reset_cause; 187 __u32 memory_lost; 188 __u32 gpu_id; 189 }; 190 struct kfd_event_data { 191 union { 192 struct kfd_hsa_memory_exception_data memory_exception_data; 193 struct kfd_hsa_hw_exception_data hw_exception_data; 194 }; 195 __u64 kfd_event_data_ext; 196 __u32 event_id; 197 __u32 pad; 198 }; 199 struct kfd_ioctl_wait_events_args { 200 __u64 events_ptr; 201 __u32 num_events; 202 __u32 wait_for_all; 203 __u32 timeout; 204 __u32 wait_result; 205 }; 206 struct kfd_ioctl_set_scratch_backing_va_args { 207 __u64 va_addr; 208 __u32 gpu_id; 209 __u32 pad; 210 }; 211 struct kfd_ioctl_get_tile_config_args { 212 __u64 tile_config_ptr; 213 __u64 macro_tile_config_ptr; 214 __u32 num_tile_configs; 215 __u32 num_macro_tile_configs; 216 __u32 gpu_id; 217 __u32 gb_addr_config; 218 __u32 num_banks; 219 __u32 num_ranks; 220 }; 221 struct kfd_ioctl_set_trap_handler_args { 222 __u64 tba_addr; 223 __u64 tma_addr; 224 __u32 gpu_id; 225 __u32 pad; 226 }; 227 struct kfd_ioctl_acquire_vm_args { 228 __u32 drm_fd; 229 __u32 gpu_id; 230 }; 231 #define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0) 232 #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1) 233 #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2) 234 #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3) 235 #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31) 236 #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30) 237 #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29) 238 #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) 239 #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27) 240 #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26) 241 struct kfd_ioctl_alloc_memory_of_gpu_args { 242 __u64 va_addr; 243 __u64 size; 244 __u64 handle; 245 __u64 mmap_offset; 246 __u32 gpu_id; 247 __u32 flags; 248 }; 249 struct kfd_ioctl_free_memory_of_gpu_args { 250 __u64 handle; 251 }; 252 struct kfd_ioctl_map_memory_to_gpu_args { 253 __u64 handle; 254 __u64 device_ids_array_ptr; 255 __u32 n_devices; 256 __u32 n_success; 257 }; 258 struct kfd_ioctl_unmap_memory_from_gpu_args { 259 __u64 handle; 260 __u64 device_ids_array_ptr; 261 __u32 n_devices; 262 __u32 n_success; 263 }; 264 struct kfd_ioctl_get_dmabuf_info_args { 265 __u64 size; 266 __u64 metadata_ptr; 267 __u32 metadata_size; 268 __u32 gpu_id; 269 __u32 flags; 270 __u32 dmabuf_fd; 271 }; 272 struct kfd_ioctl_import_dmabuf_args { 273 __u64 va_addr; 274 __u64 handle; 275 __u32 gpu_id; 276 __u32 dmabuf_fd; 277 }; 278 #define AMDKFD_IOCTL_BASE 'K' 279 #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) 280 #define AMDKFD_IOR(nr,type) _IOR(AMDKFD_IOCTL_BASE, nr, type) 281 #define AMDKFD_IOW(nr,type) _IOW(AMDKFD_IOCTL_BASE, nr, type) 282 #define AMDKFD_IOWR(nr,type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) 283 #define AMDKFD_IOC_GET_VERSION AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) 284 #define AMDKFD_IOC_CREATE_QUEUE AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) 285 #define AMDKFD_IOC_DESTROY_QUEUE AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) 286 #define AMDKFD_IOC_SET_MEMORY_POLICY AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) 287 #define AMDKFD_IOC_GET_CLOCK_COUNTERS AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) 288 #define AMDKFD_IOC_GET_PROCESS_APERTURES AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) 289 #define AMDKFD_IOC_UPDATE_QUEUE AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) 290 #define AMDKFD_IOC_CREATE_EVENT AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) 291 #define AMDKFD_IOC_DESTROY_EVENT AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) 292 #define AMDKFD_IOC_SET_EVENT AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) 293 #define AMDKFD_IOC_RESET_EVENT AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) 294 #define AMDKFD_IOC_WAIT_EVENTS AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) 295 #define AMDKFD_IOC_DBG_REGISTER AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) 296 #define AMDKFD_IOC_DBG_UNREGISTER AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) 297 #define AMDKFD_IOC_DBG_ADDRESS_WATCH AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) 298 #define AMDKFD_IOC_DBG_WAVE_CONTROL AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) 299 #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args) 300 #define AMDKFD_IOC_GET_TILE_CONFIG AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) 301 #define AMDKFD_IOC_SET_TRAP_HANDLER AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args) 302 #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW AMDKFD_IOWR(0x14, struct kfd_ioctl_get_process_apertures_new_args) 303 #define AMDKFD_IOC_ACQUIRE_VM AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args) 304 #define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args) 305 #define AMDKFD_IOC_FREE_MEMORY_OF_GPU AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args) 306 #define AMDKFD_IOC_MAP_MEMORY_TO_GPU AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args) 307 #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args) 308 #define AMDKFD_IOC_SET_CU_MASK AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args) 309 #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args) 310 #define AMDKFD_IOC_GET_DMABUF_INFO AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args) 311 #define AMDKFD_IOC_IMPORT_DMABUF AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args) 312 #define AMDKFD_COMMAND_START 0x01 313 #define AMDKFD_COMMAND_END 0x1E 314 #endif 315
