1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPIVFIO_H 20 #define _UAPIVFIO_H 21 #include <linux/types.h> 22 #include <linux/ioctl.h> 23 #define VFIO_API_VERSION 0 24 #define VFIO_TYPE1_IOMMU 1 25 #define VFIO_SPAPR_TCE_IOMMU 2 26 #define VFIO_TYPE1v2_IOMMU 3 27 #define VFIO_DMA_CC_IOMMU 4 28 #define VFIO_EEH 5 29 #define VFIO_TYPE1_NESTING_IOMMU 6 30 #define VFIO_SPAPR_TCE_v2_IOMMU 7 31 #define VFIO_NOIOMMU_IOMMU 8 32 #define VFIO_TYPE (';') 33 #define VFIO_BASE 100 34 struct vfio_info_cap_header { 35 __u16 id; 36 __u16 version; 37 __u32 next; 38 }; 39 #define VFIO_GET_API_VERSION _IO(VFIO_TYPE, VFIO_BASE + 0) 40 #define VFIO_CHECK_EXTENSION _IO(VFIO_TYPE, VFIO_BASE + 1) 41 #define VFIO_SET_IOMMU _IO(VFIO_TYPE, VFIO_BASE + 2) 42 struct vfio_group_status { 43 __u32 argsz; 44 __u32 flags; 45 #define VFIO_GROUP_FLAGS_VIABLE (1 << 0) 46 #define VFIO_GROUP_FLAGS_CONTAINER_SET (1 << 1) 47 }; 48 #define VFIO_GROUP_GET_STATUS _IO(VFIO_TYPE, VFIO_BASE + 3) 49 #define VFIO_GROUP_SET_CONTAINER _IO(VFIO_TYPE, VFIO_BASE + 4) 50 #define VFIO_GROUP_UNSET_CONTAINER _IO(VFIO_TYPE, VFIO_BASE + 5) 51 #define VFIO_GROUP_GET_DEVICE_FD _IO(VFIO_TYPE, VFIO_BASE + 6) 52 struct vfio_device_info { 53 __u32 argsz; 54 __u32 flags; 55 #define VFIO_DEVICE_FLAGS_RESET (1 << 0) 56 #define VFIO_DEVICE_FLAGS_PCI (1 << 1) 57 #define VFIO_DEVICE_FLAGS_PLATFORM (1 << 2) 58 #define VFIO_DEVICE_FLAGS_AMBA (1 << 3) 59 #define VFIO_DEVICE_FLAGS_CCW (1 << 4) 60 #define VFIO_DEVICE_FLAGS_AP (1 << 5) 61 __u32 num_regions; 62 __u32 num_irqs; 63 }; 64 #define VFIO_DEVICE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 7) 65 #define VFIO_DEVICE_API_PCI_STRING "vfio-pci" 66 #define VFIO_DEVICE_API_PLATFORM_STRING "vfio-platform" 67 #define VFIO_DEVICE_API_AMBA_STRING "vfio-amba" 68 #define VFIO_DEVICE_API_CCW_STRING "vfio-ccw" 69 #define VFIO_DEVICE_API_AP_STRING "vfio-ap" 70 struct vfio_region_info { 71 __u32 argsz; 72 __u32 flags; 73 #define VFIO_REGION_INFO_FLAG_READ (1 << 0) 74 #define VFIO_REGION_INFO_FLAG_WRITE (1 << 1) 75 #define VFIO_REGION_INFO_FLAG_MMAP (1 << 2) 76 #define VFIO_REGION_INFO_FLAG_CAPS (1 << 3) 77 __u32 index; 78 __u32 cap_offset; 79 __u64 size; 80 __u64 offset; 81 }; 82 #define VFIO_DEVICE_GET_REGION_INFO _IO(VFIO_TYPE, VFIO_BASE + 8) 83 #define VFIO_REGION_INFO_CAP_SPARSE_MMAP 1 84 struct vfio_region_sparse_mmap_area { 85 __u64 offset; 86 __u64 size; 87 }; 88 struct vfio_region_info_cap_sparse_mmap { 89 struct vfio_info_cap_header header; 90 __u32 nr_areas; 91 __u32 reserved; 92 struct vfio_region_sparse_mmap_area areas[]; 93 }; 94 #define VFIO_REGION_INFO_CAP_TYPE 2 95 struct vfio_region_info_cap_type { 96 struct vfio_info_cap_header header; 97 __u32 type; 98 __u32 subtype; 99 }; 100 #define VFIO_REGION_TYPE_PCI_VENDOR_TYPE (1 << 31) 101 #define VFIO_REGION_TYPE_PCI_VENDOR_MASK (0xffff) 102 #define VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION (1) 103 #define VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG (2) 104 #define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG (3) 105 #define VFIO_REGION_TYPE_GFX (1) 106 #define VFIO_REGION_SUBTYPE_GFX_EDID (1) 107 struct vfio_region_gfx_edid { 108 __u32 edid_offset; 109 __u32 edid_max_size; 110 __u32 edid_size; 111 __u32 max_xres; 112 __u32 max_yres; 113 __u32 link_state; 114 #define VFIO_DEVICE_GFX_LINK_STATE_UP 1 115 #define VFIO_DEVICE_GFX_LINK_STATE_DOWN 2 116 }; 117 #define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1) 118 #define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) 119 #define VFIO_REGION_INFO_CAP_MSIX_MAPPABLE 3 120 #define VFIO_REGION_INFO_CAP_NVLINK2_SSATGT 4 121 struct vfio_region_info_cap_nvlink2_ssatgt { 122 struct vfio_info_cap_header header; 123 __u64 tgt; 124 }; 125 #define VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD 5 126 struct vfio_region_info_cap_nvlink2_lnkspd { 127 struct vfio_info_cap_header header; 128 __u32 link_speed; 129 __u32 __pad; 130 }; 131 struct vfio_irq_info { 132 __u32 argsz; 133 __u32 flags; 134 #define VFIO_IRQ_INFO_EVENTFD (1 << 0) 135 #define VFIO_IRQ_INFO_MASKABLE (1 << 1) 136 #define VFIO_IRQ_INFO_AUTOMASKED (1 << 2) 137 #define VFIO_IRQ_INFO_NORESIZE (1 << 3) 138 __u32 index; 139 __u32 count; 140 }; 141 #define VFIO_DEVICE_GET_IRQ_INFO _IO(VFIO_TYPE, VFIO_BASE + 9) 142 struct vfio_irq_set { 143 __u32 argsz; 144 __u32 flags; 145 #define VFIO_IRQ_SET_DATA_NONE (1 << 0) 146 #define VFIO_IRQ_SET_DATA_BOOL (1 << 1) 147 #define VFIO_IRQ_SET_DATA_EVENTFD (1 << 2) 148 #define VFIO_IRQ_SET_ACTION_MASK (1 << 3) 149 #define VFIO_IRQ_SET_ACTION_UNMASK (1 << 4) 150 #define VFIO_IRQ_SET_ACTION_TRIGGER (1 << 5) 151 __u32 index; 152 __u32 start; 153 __u32 count; 154 __u8 data[]; 155 }; 156 #define VFIO_DEVICE_SET_IRQS _IO(VFIO_TYPE, VFIO_BASE + 10) 157 #define VFIO_IRQ_SET_DATA_TYPE_MASK (VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_DATA_BOOL | VFIO_IRQ_SET_DATA_EVENTFD) 158 #define VFIO_IRQ_SET_ACTION_TYPE_MASK (VFIO_IRQ_SET_ACTION_MASK | VFIO_IRQ_SET_ACTION_UNMASK | VFIO_IRQ_SET_ACTION_TRIGGER) 159 #define VFIO_DEVICE_RESET _IO(VFIO_TYPE, VFIO_BASE + 11) 160 enum { 161 VFIO_PCI_BAR0_REGION_INDEX, 162 VFIO_PCI_BAR1_REGION_INDEX, 163 VFIO_PCI_BAR2_REGION_INDEX, 164 VFIO_PCI_BAR3_REGION_INDEX, 165 VFIO_PCI_BAR4_REGION_INDEX, 166 VFIO_PCI_BAR5_REGION_INDEX, 167 VFIO_PCI_ROM_REGION_INDEX, 168 VFIO_PCI_CONFIG_REGION_INDEX, 169 VFIO_PCI_VGA_REGION_INDEX, 170 VFIO_PCI_NUM_REGIONS = 9 171 }; 172 enum { 173 VFIO_PCI_INTX_IRQ_INDEX, 174 VFIO_PCI_MSI_IRQ_INDEX, 175 VFIO_PCI_MSIX_IRQ_INDEX, 176 VFIO_PCI_ERR_IRQ_INDEX, 177 VFIO_PCI_REQ_IRQ_INDEX, 178 VFIO_PCI_NUM_IRQS 179 }; 180 enum { 181 VFIO_CCW_CONFIG_REGION_INDEX, 182 VFIO_CCW_NUM_REGIONS 183 }; 184 enum { 185 VFIO_CCW_IO_IRQ_INDEX, 186 VFIO_CCW_NUM_IRQS 187 }; 188 struct vfio_pci_dependent_device { 189 __u32 group_id; 190 __u16 segment; 191 __u8 bus; 192 __u8 devfn; 193 }; 194 struct vfio_pci_hot_reset_info { 195 __u32 argsz; 196 __u32 flags; 197 __u32 count; 198 struct vfio_pci_dependent_device devices[]; 199 }; 200 #define VFIO_DEVICE_GET_PCI_HOT_RESET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) 201 struct vfio_pci_hot_reset { 202 __u32 argsz; 203 __u32 flags; 204 __u32 count; 205 __s32 group_fds[]; 206 }; 207 #define VFIO_DEVICE_PCI_HOT_RESET _IO(VFIO_TYPE, VFIO_BASE + 13) 208 struct vfio_device_gfx_plane_info { 209 __u32 argsz; 210 __u32 flags; 211 #define VFIO_GFX_PLANE_TYPE_PROBE (1 << 0) 212 #define VFIO_GFX_PLANE_TYPE_DMABUF (1 << 1) 213 #define VFIO_GFX_PLANE_TYPE_REGION (1 << 2) 214 __u32 drm_plane_type; 215 __u32 drm_format; 216 __u64 drm_format_mod; 217 __u32 width; 218 __u32 height; 219 __u32 stride; 220 __u32 size; 221 __u32 x_pos; 222 __u32 y_pos; 223 __u32 x_hot; 224 __u32 y_hot; 225 union { 226 __u32 region_index; 227 __u32 dmabuf_id; 228 }; 229 }; 230 #define VFIO_DEVICE_QUERY_GFX_PLANE _IO(VFIO_TYPE, VFIO_BASE + 14) 231 #define VFIO_DEVICE_GET_GFX_DMABUF _IO(VFIO_TYPE, VFIO_BASE + 15) 232 struct vfio_device_ioeventfd { 233 __u32 argsz; 234 __u32 flags; 235 #define VFIO_DEVICE_IOEVENTFD_8 (1 << 0) 236 #define VFIO_DEVICE_IOEVENTFD_16 (1 << 1) 237 #define VFIO_DEVICE_IOEVENTFD_32 (1 << 2) 238 #define VFIO_DEVICE_IOEVENTFD_64 (1 << 3) 239 #define VFIO_DEVICE_IOEVENTFD_SIZE_MASK (0xf) 240 __u64 offset; 241 __u64 data; 242 __s32 fd; 243 }; 244 #define VFIO_DEVICE_IOEVENTFD _IO(VFIO_TYPE, VFIO_BASE + 16) 245 struct vfio_iommu_type1_info { 246 __u32 argsz; 247 __u32 flags; 248 #define VFIO_IOMMU_INFO_PGSIZES (1 << 0) 249 __u64 iova_pgsizes; 250 }; 251 #define VFIO_IOMMU_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) 252 struct vfio_iommu_type1_dma_map { 253 __u32 argsz; 254 __u32 flags; 255 #define VFIO_DMA_MAP_FLAG_READ (1 << 0) 256 #define VFIO_DMA_MAP_FLAG_WRITE (1 << 1) 257 __u64 vaddr; 258 __u64 iova; 259 __u64 size; 260 }; 261 #define VFIO_IOMMU_MAP_DMA _IO(VFIO_TYPE, VFIO_BASE + 13) 262 struct vfio_iommu_type1_dma_unmap { 263 __u32 argsz; 264 __u32 flags; 265 __u64 iova; 266 __u64 size; 267 }; 268 #define VFIO_IOMMU_UNMAP_DMA _IO(VFIO_TYPE, VFIO_BASE + 14) 269 #define VFIO_IOMMU_ENABLE _IO(VFIO_TYPE, VFIO_BASE + 15) 270 #define VFIO_IOMMU_DISABLE _IO(VFIO_TYPE, VFIO_BASE + 16) 271 struct vfio_iommu_spapr_tce_ddw_info { 272 __u64 pgsizes; 273 __u32 max_dynamic_windows_supported; 274 __u32 levels; 275 }; 276 struct vfio_iommu_spapr_tce_info { 277 __u32 argsz; 278 __u32 flags; 279 #define VFIO_IOMMU_SPAPR_INFO_DDW (1 << 0) 280 __u32 dma32_window_start; 281 __u32 dma32_window_size; 282 struct vfio_iommu_spapr_tce_ddw_info ddw; 283 }; 284 #define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) 285 struct vfio_eeh_pe_err { 286 __u32 type; 287 __u32 func; 288 __u64 addr; 289 __u64 mask; 290 }; 291 struct vfio_eeh_pe_op { 292 __u32 argsz; 293 __u32 flags; 294 __u32 op; 295 union { 296 struct vfio_eeh_pe_err err; 297 }; 298 }; 299 #define VFIO_EEH_PE_DISABLE 0 300 #define VFIO_EEH_PE_ENABLE 1 301 #define VFIO_EEH_PE_UNFREEZE_IO 2 302 #define VFIO_EEH_PE_UNFREEZE_DMA 3 303 #define VFIO_EEH_PE_GET_STATE 4 304 #define VFIO_EEH_PE_STATE_NORMAL 0 305 #define VFIO_EEH_PE_STATE_RESET 1 306 #define VFIO_EEH_PE_STATE_STOPPED 2 307 #define VFIO_EEH_PE_STATE_STOPPED_DMA 4 308 #define VFIO_EEH_PE_STATE_UNAVAIL 5 309 #define VFIO_EEH_PE_RESET_DEACTIVATE 5 310 #define VFIO_EEH_PE_RESET_HOT 6 311 #define VFIO_EEH_PE_RESET_FUNDAMENTAL 7 312 #define VFIO_EEH_PE_CONFIGURE 8 313 #define VFIO_EEH_PE_INJECT_ERR 9 314 #define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21) 315 struct vfio_iommu_spapr_register_memory { 316 __u32 argsz; 317 __u32 flags; 318 __u64 vaddr; 319 __u64 size; 320 }; 321 #define VFIO_IOMMU_SPAPR_REGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 17) 322 #define VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 18) 323 struct vfio_iommu_spapr_tce_create { 324 __u32 argsz; 325 __u32 flags; 326 __u32 page_shift; 327 __u32 __resv1; 328 __u64 window_size; 329 __u32 levels; 330 __u32 __resv2; 331 __u64 start_addr; 332 }; 333 #define VFIO_IOMMU_SPAPR_TCE_CREATE _IO(VFIO_TYPE, VFIO_BASE + 19) 334 struct vfio_iommu_spapr_tce_remove { 335 __u32 argsz; 336 __u32 flags; 337 __u64 start_addr; 338 }; 339 #define VFIO_IOMMU_SPAPR_TCE_REMOVE _IO(VFIO_TYPE, VFIO_BASE + 20) 340 #endif 341
