1 /*- 2 * Copyright (c) 2004-2005 David Schultz <das (at) FreeBSD.ORG> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $ 27 */ 28 29 #pragma once 30 31 #include <sys/types.h> 32 33 __BEGIN_DECLS 34 35 /* 36 * The ARM Cortex-A75 registers are described here: 37 * 38 * AArch64: 39 * FPCR: http://infocenter.arm.com/help/topic/com.arm.doc.100403_0200_00_en/lau1442502503726.html 40 * FPSR: http://infocenter.arm.com/help/topic/com.arm.doc.100403_0200_00_en/lau1442502526288.html 41 * AArch32: 42 * FPSCR: http://infocenter.arm.com/help/topic/com.arm.doc.100403_0200_00_en/lau1442504290459.html 43 */ 44 45 #if defined(__LP64__) 46 typedef struct { 47 /* FPCR, Floating-point Control Register. */ 48 __uint32_t __control; 49 /* FPSR, Floating-point Status Register. */ 50 __uint32_t __status; 51 } fenv_t; 52 53 #else 54 typedef __uint32_t fenv_t; 55 #endif 56 57 typedef __uint32_t fexcept_t; 58 59 /* Exception flags. */ 60 #define FE_INVALID 0x01 61 #define FE_DIVBYZERO 0x02 62 #define FE_OVERFLOW 0x04 63 #define FE_UNDERFLOW 0x08 64 #define FE_INEXACT 0x10 65 #define FE_DENORMAL 0x80 66 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW | FE_DENORMAL) 67 68 /* Rounding modes. */ 69 #define FE_TONEAREST 0x0 70 #define FE_UPWARD 0x1 71 #define FE_DOWNWARD 0x2 72 #define FE_TOWARDZERO 0x3 73 74 __END_DECLS 75
