1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __AMDGPU_DRM_H__ 20 #define __AMDGPU_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define DRM_AMDGPU_GEM_CREATE 0x00 26 #define DRM_AMDGPU_GEM_MMAP 0x01 27 #define DRM_AMDGPU_CTX 0x02 28 #define DRM_AMDGPU_BO_LIST 0x03 29 #define DRM_AMDGPU_CS 0x04 30 #define DRM_AMDGPU_INFO 0x05 31 #define DRM_AMDGPU_GEM_METADATA 0x06 32 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 33 #define DRM_AMDGPU_GEM_VA 0x08 34 #define DRM_AMDGPU_WAIT_CS 0x09 35 #define DRM_AMDGPU_GEM_OP 0x10 36 #define DRM_AMDGPU_GEM_USERPTR 0x11 37 #define DRM_AMDGPU_WAIT_FENCES 0x12 38 #define DRM_AMDGPU_VM 0x13 39 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 40 #define DRM_AMDGPU_SCHED 0x15 41 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 42 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 43 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 44 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 45 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 46 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 47 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 48 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 49 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 50 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 51 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 52 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 53 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 54 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 55 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 56 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 57 #define AMDGPU_GEM_DOMAIN_CPU 0x1 58 #define AMDGPU_GEM_DOMAIN_GTT 0x2 59 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 60 #define AMDGPU_GEM_DOMAIN_GDS 0x8 61 #define AMDGPU_GEM_DOMAIN_GWS 0x10 62 #define AMDGPU_GEM_DOMAIN_OA 0x20 63 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA) 64 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 65 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 66 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 67 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 68 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 69 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 70 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 71 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 72 #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) 73 struct drm_amdgpu_gem_create_in { 74 __u64 bo_size; 75 __u64 alignment; 76 __u64 domains; 77 __u64 domain_flags; 78 }; 79 struct drm_amdgpu_gem_create_out { 80 __u32 handle; 81 __u32 _pad; 82 }; 83 union drm_amdgpu_gem_create { 84 struct drm_amdgpu_gem_create_in in; 85 struct drm_amdgpu_gem_create_out out; 86 }; 87 #define AMDGPU_BO_LIST_OP_CREATE 0 88 #define AMDGPU_BO_LIST_OP_DESTROY 1 89 #define AMDGPU_BO_LIST_OP_UPDATE 2 90 struct drm_amdgpu_bo_list_in { 91 __u32 operation; 92 __u32 list_handle; 93 __u32 bo_number; 94 __u32 bo_info_size; 95 __u64 bo_info_ptr; 96 }; 97 struct drm_amdgpu_bo_list_entry { 98 __u32 bo_handle; 99 __u32 bo_priority; 100 }; 101 struct drm_amdgpu_bo_list_out { 102 __u32 list_handle; 103 __u32 _pad; 104 }; 105 union drm_amdgpu_bo_list { 106 struct drm_amdgpu_bo_list_in in; 107 struct drm_amdgpu_bo_list_out out; 108 }; 109 #define AMDGPU_CTX_OP_ALLOC_CTX 1 110 #define AMDGPU_CTX_OP_FREE_CTX 2 111 #define AMDGPU_CTX_OP_QUERY_STATE 3 112 #define AMDGPU_CTX_OP_QUERY_STATE2 4 113 #define AMDGPU_CTX_NO_RESET 0 114 #define AMDGPU_CTX_GUILTY_RESET 1 115 #define AMDGPU_CTX_INNOCENT_RESET 2 116 #define AMDGPU_CTX_UNKNOWN_RESET 3 117 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1 << 0) 118 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1 << 1) 119 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1 << 2) 120 #define AMDGPU_CTX_PRIORITY_UNSET - 2048 121 #define AMDGPU_CTX_PRIORITY_VERY_LOW - 1023 122 #define AMDGPU_CTX_PRIORITY_LOW - 512 123 #define AMDGPU_CTX_PRIORITY_NORMAL 0 124 #define AMDGPU_CTX_PRIORITY_HIGH 512 125 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 126 struct drm_amdgpu_ctx_in { 127 __u32 op; 128 __u32 flags; 129 __u32 ctx_id; 130 __s32 priority; 131 }; 132 union drm_amdgpu_ctx_out { 133 struct { 134 __u32 ctx_id; 135 __u32 _pad; 136 } alloc; 137 struct { 138 __u64 flags; 139 __u32 hangs; 140 __u32 reset_status; 141 } state; 142 }; 143 union drm_amdgpu_ctx { 144 struct drm_amdgpu_ctx_in in; 145 union drm_amdgpu_ctx_out out; 146 }; 147 #define AMDGPU_VM_OP_RESERVE_VMID 1 148 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 149 struct drm_amdgpu_vm_in { 150 __u32 op; 151 __u32 flags; 152 }; 153 struct drm_amdgpu_vm_out { 154 __u64 flags; 155 }; 156 union drm_amdgpu_vm { 157 struct drm_amdgpu_vm_in in; 158 struct drm_amdgpu_vm_out out; 159 }; 160 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 161 struct drm_amdgpu_sched_in { 162 __u32 op; 163 __u32 fd; 164 __s32 priority; 165 __u32 flags; 166 }; 167 union drm_amdgpu_sched { 168 struct drm_amdgpu_sched_in in; 169 }; 170 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 171 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 172 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 173 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 174 struct drm_amdgpu_gem_userptr { 175 __u64 addr; 176 __u64 size; 177 __u32 flags; 178 __u32 handle; 179 }; 180 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 181 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 182 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 183 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 184 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 185 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 186 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 187 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 188 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 189 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 190 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 191 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 192 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 193 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 194 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 195 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 196 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 197 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 198 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 199 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 200 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 201 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 202 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 203 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 204 #define AMDGPU_TILING_SET(field,value) (((__u64) (value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT) 205 #define AMDGPU_TILING_GET(value,field) (((__u64) (value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK) 206 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 207 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 208 struct drm_amdgpu_gem_metadata { 209 __u32 handle; 210 __u32 op; 211 struct { 212 __u64 flags; 213 __u64 tiling_info; 214 __u32 data_size_bytes; 215 __u32 data[64]; 216 } data; 217 }; 218 struct drm_amdgpu_gem_mmap_in { 219 __u32 handle; 220 __u32 _pad; 221 }; 222 struct drm_amdgpu_gem_mmap_out { 223 __u64 addr_ptr; 224 }; 225 union drm_amdgpu_gem_mmap { 226 struct drm_amdgpu_gem_mmap_in in; 227 struct drm_amdgpu_gem_mmap_out out; 228 }; 229 struct drm_amdgpu_gem_wait_idle_in { 230 __u32 handle; 231 __u32 flags; 232 __u64 timeout; 233 }; 234 struct drm_amdgpu_gem_wait_idle_out { 235 __u32 status; 236 __u32 domain; 237 }; 238 union drm_amdgpu_gem_wait_idle { 239 struct drm_amdgpu_gem_wait_idle_in in; 240 struct drm_amdgpu_gem_wait_idle_out out; 241 }; 242 struct drm_amdgpu_wait_cs_in { 243 __u64 handle; 244 __u64 timeout; 245 __u32 ip_type; 246 __u32 ip_instance; 247 __u32 ring; 248 __u32 ctx_id; 249 }; 250 struct drm_amdgpu_wait_cs_out { 251 __u64 status; 252 }; 253 union drm_amdgpu_wait_cs { 254 struct drm_amdgpu_wait_cs_in in; 255 struct drm_amdgpu_wait_cs_out out; 256 }; 257 struct drm_amdgpu_fence { 258 __u32 ctx_id; 259 __u32 ip_type; 260 __u32 ip_instance; 261 __u32 ring; 262 __u64 seq_no; 263 }; 264 struct drm_amdgpu_wait_fences_in { 265 __u64 fences; 266 __u32 fence_count; 267 __u32 wait_all; 268 __u64 timeout_ns; 269 }; 270 struct drm_amdgpu_wait_fences_out { 271 __u32 status; 272 __u32 first_signaled; 273 }; 274 union drm_amdgpu_wait_fences { 275 struct drm_amdgpu_wait_fences_in in; 276 struct drm_amdgpu_wait_fences_out out; 277 }; 278 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 279 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 280 struct drm_amdgpu_gem_op { 281 __u32 handle; 282 __u32 op; 283 __u64 value; 284 }; 285 #define AMDGPU_VA_OP_MAP 1 286 #define AMDGPU_VA_OP_UNMAP 2 287 #define AMDGPU_VA_OP_CLEAR 3 288 #define AMDGPU_VA_OP_REPLACE 4 289 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 290 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 291 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 292 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 293 #define AMDGPU_VM_PAGE_PRT (1 << 4) 294 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 295 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 296 #define AMDGPU_VM_MTYPE_NC (1 << 5) 297 #define AMDGPU_VM_MTYPE_WC (2 << 5) 298 #define AMDGPU_VM_MTYPE_CC (3 << 5) 299 #define AMDGPU_VM_MTYPE_UC (4 << 5) 300 struct drm_amdgpu_gem_va { 301 __u32 handle; 302 __u32 _pad; 303 __u32 operation; 304 __u32 flags; 305 __u64 va_address; 306 __u64 offset_in_bo; 307 __u64 map_size; 308 }; 309 #define AMDGPU_HW_IP_GFX 0 310 #define AMDGPU_HW_IP_COMPUTE 1 311 #define AMDGPU_HW_IP_DMA 2 312 #define AMDGPU_HW_IP_UVD 3 313 #define AMDGPU_HW_IP_VCE 4 314 #define AMDGPU_HW_IP_UVD_ENC 5 315 #define AMDGPU_HW_IP_VCN_DEC 6 316 #define AMDGPU_HW_IP_VCN_ENC 7 317 #define AMDGPU_HW_IP_VCN_JPEG 8 318 #define AMDGPU_HW_IP_NUM 9 319 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 320 #define AMDGPU_CHUNK_ID_IB 0x01 321 #define AMDGPU_CHUNK_ID_FENCE 0x02 322 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 323 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 324 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 325 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 326 struct drm_amdgpu_cs_chunk { 327 __u32 chunk_id; 328 __u32 length_dw; 329 __u64 chunk_data; 330 }; 331 struct drm_amdgpu_cs_in { 332 __u32 ctx_id; 333 __u32 bo_list_handle; 334 __u32 num_chunks; 335 __u32 _pad; 336 __u64 chunks; 337 }; 338 struct drm_amdgpu_cs_out { 339 __u64 handle; 340 }; 341 union drm_amdgpu_cs { 342 struct drm_amdgpu_cs_in in; 343 struct drm_amdgpu_cs_out out; 344 }; 345 #define AMDGPU_IB_FLAG_CE (1 << 0) 346 #define AMDGPU_IB_FLAG_PREAMBLE (1 << 1) 347 #define AMDGPU_IB_FLAG_PREEMPT (1 << 2) 348 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 349 struct drm_amdgpu_cs_chunk_ib { 350 __u32 _pad; 351 __u32 flags; 352 __u64 va_start; 353 __u32 ib_bytes; 354 __u32 ip_type; 355 __u32 ip_instance; 356 __u32 ring; 357 }; 358 struct drm_amdgpu_cs_chunk_dep { 359 __u32 ip_type; 360 __u32 ip_instance; 361 __u32 ring; 362 __u32 ctx_id; 363 __u64 handle; 364 }; 365 struct drm_amdgpu_cs_chunk_fence { 366 __u32 handle; 367 __u32 offset; 368 }; 369 struct drm_amdgpu_cs_chunk_sem { 370 __u32 handle; 371 }; 372 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 373 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 374 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 375 union drm_amdgpu_fence_to_handle { 376 struct { 377 struct drm_amdgpu_fence fence; 378 __u32 what; 379 __u32 pad; 380 } in; 381 struct { 382 __u32 handle; 383 } out; 384 }; 385 struct drm_amdgpu_cs_chunk_data { 386 union { 387 struct drm_amdgpu_cs_chunk_ib ib_data; 388 struct drm_amdgpu_cs_chunk_fence fence_data; 389 }; 390 }; 391 #define AMDGPU_IDS_FLAGS_FUSION 0x1 392 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 393 #define AMDGPU_INFO_ACCEL_WORKING 0x00 394 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 395 #define AMDGPU_INFO_HW_IP_INFO 0x02 396 #define AMDGPU_INFO_HW_IP_COUNT 0x03 397 #define AMDGPU_INFO_TIMESTAMP 0x05 398 #define AMDGPU_INFO_FW_VERSION 0x0e 399 #define AMDGPU_INFO_FW_VCE 0x1 400 #define AMDGPU_INFO_FW_UVD 0x2 401 #define AMDGPU_INFO_FW_GMC 0x03 402 #define AMDGPU_INFO_FW_GFX_ME 0x04 403 #define AMDGPU_INFO_FW_GFX_PFP 0x05 404 #define AMDGPU_INFO_FW_GFX_CE 0x06 405 #define AMDGPU_INFO_FW_GFX_RLC 0x07 406 #define AMDGPU_INFO_FW_GFX_MEC 0x08 407 #define AMDGPU_INFO_FW_SMC 0x0a 408 #define AMDGPU_INFO_FW_SDMA 0x0b 409 #define AMDGPU_INFO_FW_SOS 0x0c 410 #define AMDGPU_INFO_FW_ASD 0x0d 411 #define AMDGPU_INFO_FW_VCN 0x0e 412 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 413 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 414 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 415 #define AMDGPU_INFO_FW_DMCU 0x12 416 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 417 #define AMDGPU_INFO_VRAM_USAGE 0x10 418 #define AMDGPU_INFO_GTT_USAGE 0x11 419 #define AMDGPU_INFO_GDS_CONFIG 0x13 420 #define AMDGPU_INFO_VRAM_GTT 0x14 421 #define AMDGPU_INFO_READ_MMR_REG 0x15 422 #define AMDGPU_INFO_DEV_INFO 0x16 423 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 424 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 425 #define AMDGPU_INFO_MEMORY 0x19 426 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 427 #define AMDGPU_INFO_VBIOS 0x1B 428 #define AMDGPU_INFO_VBIOS_SIZE 0x1 429 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 430 #define AMDGPU_INFO_NUM_HANDLES 0x1C 431 #define AMDGPU_INFO_SENSOR 0x1D 432 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 433 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 434 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 435 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 436 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 437 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 438 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 439 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 440 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 441 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 442 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 443 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 444 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 445 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 446 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 447 struct drm_amdgpu_query_fw { 448 __u32 fw_type; 449 __u32 ip_instance; 450 __u32 index; 451 __u32 _pad; 452 }; 453 struct drm_amdgpu_info { 454 __u64 return_pointer; 455 __u32 return_size; 456 __u32 query; 457 union { 458 struct { 459 __u32 id; 460 __u32 _pad; 461 } mode_crtc; 462 struct { 463 __u32 type; 464 __u32 ip_instance; 465 } query_hw_ip; 466 struct { 467 __u32 dword_offset; 468 __u32 count; 469 __u32 instance; 470 __u32 flags; 471 } read_mmr_reg; 472 struct drm_amdgpu_query_fw query_fw; 473 struct { 474 __u32 type; 475 __u32 offset; 476 } vbios_info; 477 struct { 478 __u32 type; 479 } sensor_info; 480 }; 481 }; 482 struct drm_amdgpu_info_gds { 483 __u32 gds_gfx_partition_size; 484 __u32 compute_partition_size; 485 __u32 gds_total_size; 486 __u32 gws_per_gfx_partition; 487 __u32 gws_per_compute_partition; 488 __u32 oa_per_gfx_partition; 489 __u32 oa_per_compute_partition; 490 __u32 _pad; 491 }; 492 struct drm_amdgpu_info_vram_gtt { 493 __u64 vram_size; 494 __u64 vram_cpu_accessible_size; 495 __u64 gtt_size; 496 }; 497 struct drm_amdgpu_heap_info { 498 __u64 total_heap_size; 499 __u64 usable_heap_size; 500 __u64 heap_usage; 501 __u64 max_allocation; 502 }; 503 struct drm_amdgpu_memory_info { 504 struct drm_amdgpu_heap_info vram; 505 struct drm_amdgpu_heap_info cpu_accessible_vram; 506 struct drm_amdgpu_heap_info gtt; 507 }; 508 struct drm_amdgpu_info_firmware { 509 __u32 ver; 510 __u32 feature; 511 }; 512 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 513 #define AMDGPU_VRAM_TYPE_GDDR1 1 514 #define AMDGPU_VRAM_TYPE_DDR2 2 515 #define AMDGPU_VRAM_TYPE_GDDR3 3 516 #define AMDGPU_VRAM_TYPE_GDDR4 4 517 #define AMDGPU_VRAM_TYPE_GDDR5 5 518 #define AMDGPU_VRAM_TYPE_HBM 6 519 #define AMDGPU_VRAM_TYPE_DDR3 7 520 #define AMDGPU_VRAM_TYPE_DDR4 8 521 struct drm_amdgpu_info_device { 522 __u32 device_id; 523 __u32 chip_rev; 524 __u32 external_rev; 525 __u32 pci_rev; 526 __u32 family; 527 __u32 num_shader_engines; 528 __u32 num_shader_arrays_per_engine; 529 __u32 gpu_counter_freq; 530 __u64 max_engine_clock; 531 __u64 max_memory_clock; 532 __u32 cu_active_number; 533 __u32 cu_ao_mask; 534 __u32 cu_bitmap[4][4]; 535 __u32 enabled_rb_pipes_mask; 536 __u32 num_rb_pipes; 537 __u32 num_hw_gfx_contexts; 538 __u32 _pad; 539 __u64 ids_flags; 540 __u64 virtual_address_offset; 541 __u64 virtual_address_max; 542 __u32 virtual_address_alignment; 543 __u32 pte_fragment_size; 544 __u32 gart_page_size; 545 __u32 ce_ram_size; 546 __u32 vram_type; 547 __u32 vram_bit_width; 548 __u32 vce_harvest_config; 549 __u32 gc_double_offchip_lds_buf; 550 __u64 prim_buf_gpu_addr; 551 __u64 pos_buf_gpu_addr; 552 __u64 cntl_sb_buf_gpu_addr; 553 __u64 param_buf_gpu_addr; 554 __u32 prim_buf_size; 555 __u32 pos_buf_size; 556 __u32 cntl_sb_buf_size; 557 __u32 param_buf_size; 558 __u32 wave_front_size; 559 __u32 num_shader_visible_vgprs; 560 __u32 num_cu_per_sh; 561 __u32 num_tcc_blocks; 562 __u32 gs_vgt_table_depth; 563 __u32 gs_prim_buffer_depth; 564 __u32 max_gs_waves_per_vgt; 565 __u32 _pad1; 566 __u32 cu_ao_bitmap[4][4]; 567 __u64 high_va_offset; 568 __u64 high_va_max; 569 }; 570 struct drm_amdgpu_info_hw_ip { 571 __u32 hw_ip_version_major; 572 __u32 hw_ip_version_minor; 573 __u64 capabilities_flags; 574 __u32 ib_start_alignment; 575 __u32 ib_size_alignment; 576 __u32 available_rings; 577 __u32 _pad; 578 }; 579 struct drm_amdgpu_info_num_handles { 580 __u32 uvd_max_handles; 581 __u32 uvd_used_handles; 582 }; 583 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 584 struct drm_amdgpu_info_vce_clock_table_entry { 585 __u32 sclk; 586 __u32 mclk; 587 __u32 eclk; 588 __u32 pad; 589 }; 590 struct drm_amdgpu_info_vce_clock_table { 591 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 592 __u32 num_valid_entries; 593 __u32 pad; 594 }; 595 #define AMDGPU_FAMILY_UNKNOWN 0 596 #define AMDGPU_FAMILY_SI 110 597 #define AMDGPU_FAMILY_CI 120 598 #define AMDGPU_FAMILY_KV 125 599 #define AMDGPU_FAMILY_VI 130 600 #define AMDGPU_FAMILY_CZ 135 601 #define AMDGPU_FAMILY_AI 141 602 #define AMDGPU_FAMILY_RV 142 603 #ifdef __cplusplus 604 } 605 #endif 606 #endif 607
