1 /** 2 * Copyright (C) 2018 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions vand 14 * limitations under the License. 15 */ 16 #include <sys/types.h> 17 #ifndef IPA_QMI_SERVICE_V01_H 18 #define IPA_QMI_SERVICE_V01_H 19 20 #define QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01 2 21 #define QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01 2 22 #define QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01 2 23 #define QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01 2 24 #define QMI_IPA_MAX_FILTERS_V01 64 25 26 #define IPA_INT_MAX ((int)(~0U >> 1)) 27 #define IPA_INT_MIN (-IPA_INT_MAX - 1) 28 29 enum ipa_qmi_result_type_v01 { 30 IPA_QMI_RESULT_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, 31 IPA_QMI_RESULT_SUCCESS_V01 = 0, 32 IPA_QMI_RESULT_FAILURE_V01 = 1, 33 IPA_QMI_RESULT_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, 34 }; 35 36 enum ipa_qmi_error_type_v01 { 37 IPA_QMI_ERROR_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, 38 IPA_QMI_ERR_NONE_V01 = 0x0000, 39 IPA_QMI_ERR_MALFORMED_MSG_V01 = 0x0001, 40 IPA_QMI_ERR_NO_MEMORY_V01 = 0x0002, 41 IPA_QMI_ERR_INTERNAL_V01 = 0x0003, 42 IPA_QMI_ERR_CLIENT_IDS_EXHAUSTED_V01 = 0x0005, 43 IPA_QMI_ERR_INVALID_ID_V01 = 0x0029, 44 IPA_QMI_ERR_ENCODING_V01 = 0x003A, 45 IPA_QMI_ERR_INCOMPATIBLE_STATE_V01 = 0x005A, 46 IPA_QMI_ERR_NOT_SUPPORTED_V01 = 0x005E, 47 IPA_QMI_ERROR_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, 48 }; 49 50 struct ipa_qmi_response_type_v01 { 51 enum ipa_qmi_result_type_v01 result; 52 enum ipa_qmi_error_type_v01 error; 53 }; 54 55 enum ipa_platform_type_enum_v01 { 56 IPA_PLATFORM_TYPE_ENUM_MIN_ENUM_VAL_V01 = -2147483647, 57 QMI_IPA_PLATFORM_TYPE_INVALID_V01 = 0, 58 QMI_IPA_PLATFORM_TYPE_TN_V01 = 1, 59 QMI_IPA_PLATFORM_TYPE_LE_V01 = 2, 60 QMI_IPA_PLATFORM_TYPE_MSM_ANDROID_V01 = 3, 61 QMI_IPA_PLATFORM_TYPE_MSM_WINDOWS_V01 = 4, 62 QMI_IPA_PLATFORM_TYPE_MSM_QNX_V01 = 5, 63 IPA_PLATFORM_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 64 }; 65 66 struct ipa_hdr_tbl_info_type_v01 { 67 uint32_t modem_offset_start; 68 uint32_t modem_offset_end; 69 }; 70 71 struct ipa_route_tbl_info_type_v01 { 72 uint32_t route_tbl_start_addr; 73 uint32_t num_indices; 74 }; 75 76 struct ipa_modem_mem_info_type_v01 { 77 uint32_t block_start_addr; 78 uint32_t size; 79 }; 80 81 struct ipa_hdr_proc_ctx_tbl_info_type_v01 { 82 uint32_t modem_offset_start; 83 uint32_t modem_offset_end; 84 }; 85 86 struct ipa_zip_tbl_info_type_v01 { 87 uint32_t modem_offset_start; 88 uint32_t modem_offset_end; 89 }; 90 91 struct ipa_init_modem_driver_req_msg_v01 { 92 uint8_t platform_type_valid; 93 enum ipa_platform_type_enum_v01 platform_type; 94 uint8_t hdr_tbl_info_valid; 95 struct ipa_hdr_tbl_info_type_v01 hdr_tbl_info; 96 uint8_t v4_route_tbl_info_valid; 97 struct ipa_route_tbl_info_type_v01 v4_route_tbl_info; 98 uint8_t v6_route_tbl_info_valid; 99 struct ipa_route_tbl_info_type_v01 v6_route_tbl_info; 100 uint8_t v4_filter_tbl_start_addr_valid; 101 uint32_t v4_filter_tbl_start_addr; 102 uint8_t v6_filter_tbl_start_addr_valid; 103 uint32_t v6_filter_tbl_start_addr; 104 uint8_t modem_mem_info_valid; 105 struct ipa_modem_mem_info_type_v01 modem_mem_info; 106 uint8_t ctrl_comm_dest_end_pt_valid; 107 uint32_t ctrl_comm_dest_end_pt; 108 uint8_t is_ssr_bootup_valid; 109 uint8_t is_ssr_bootup; 110 uint8_t hdr_proc_ctx_tbl_info_valid; 111 struct ipa_hdr_proc_ctx_tbl_info_type_v01 hdr_proc_ctx_tbl_info; 112 uint8_t zip_tbl_info_valid; 113 struct ipa_zip_tbl_info_type_v01 zip_tbl_info; 114 }; 115 116 struct ipa_init_modem_driver_resp_msg_v01 { 117 struct ipa_qmi_response_type_v01 resp; 118 uint8_t ctrl_comm_dest_end_pt_valid; 119 uint32_t ctrl_comm_dest_end_pt; 120 uint8_t default_end_pt_valid; 121 uint32_t default_end_pt; 122 }; 123 124 struct ipa_indication_reg_req_msg_v01 { 125 uint8_t master_driver_init_complete_valid; 126 uint8_t master_driver_init_complete; 127 }; 128 129 struct ipa_indication_reg_resp_msg_v01 { 130 struct ipa_qmi_response_type_v01 resp; 131 }; 132 133 struct ipa_master_driver_init_complt_ind_msg_v01 { 134 struct ipa_qmi_response_type_v01 master_driver_init_status; 135 }; 136 137 struct ipa_ipfltr_range_eq_16_type_v01 { 138 uint8_t offset; 139 uint16_t range_low; 140 uint16_t range_high; 141 }; 142 143 struct ipa_ipfltr_mask_eq_32_type_v01 { 144 uint8_t offset; 145 uint32_t mask; 146 uint32_t value; 147 }; 148 149 struct ipa_ipfltr_eq_16_type_v01 { 150 uint8_t offset; 151 uint16_t value; 152 }; 153 154 struct ipa_ipfltr_eq_32_type_v01 { 155 uint8_t offset; 156 uint32_t value; 157 }; 158 159 struct ipa_ipfltr_mask_eq_128_type_v01 { 160 uint8_t offset; 161 uint8_t mask[16]; 162 uint8_t value[16]; 163 }; 164 165 struct ipa_filter_rule_type_v01 { 166 uint16_t rule_eq_bitmap; 167 uint8_t tos_eq_present; 168 uint8_t tos_eq; 169 uint8_t protocol_eq_present; 170 uint8_t protocol_eq; 171 uint8_t num_ihl_offset_range_16; 172 173 struct ipa_ipfltr_range_eq_16_type_v01 174 ihl_offset_range_16[QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01]; 175 176 uint8_t num_offset_meq_32; 177 178 struct ipa_ipfltr_mask_eq_32_type_v01 179 offset_meq_32[QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01]; 180 181 uint8_t tc_eq_present; 182 uint8_t tc_eq; 183 uint8_t flow_eq_present; 184 uint32_t flow_eq; 185 uint8_t ihl_offset_eq_16_present; 186 struct ipa_ipfltr_eq_16_type_v01 ihl_offset_eq_16; 187 uint8_t ihl_offset_eq_32_present; 188 struct ipa_ipfltr_eq_32_type_v01 ihl_offset_eq_32; 189 uint8_t num_ihl_offset_meq_32; 190 struct ipa_ipfltr_mask_eq_32_type_v01 191 ihl_offset_meq_32[QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01]; 192 uint8_t num_offset_meq_128; 193 struct ipa_ipfltr_mask_eq_128_type_v01 194 offset_meq_128[QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01]; 195 196 uint8_t metadata_meq32_present; 197 198 struct ipa_ipfltr_mask_eq_32_type_v01 metadata_meq32; 199 uint8_t ipv4_frag_eq_present; 200 }; 201 202 enum ipa_ip_type_enum_v01 { 203 IPA_IP_TYPE_ENUM_MIN_ENUM_VAL_V01 = -2147483647, 204 QMI_IPA_IP_TYPE_INVALID_V01 = 0, 205 QMI_IPA_IP_TYPE_V4_V01 = 1, 206 QMI_IPA_IP_TYPE_V6_V01 = 2, 207 QMI_IPA_IP_TYPE_V4V6_V01 = 3, 208 IPA_IP_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 209 }; 210 211 enum ipa_filter_action_enum_v01 { 212 IPA_FILTER_ACTION_ENUM_MIN_ENUM_VAL_V01 = -2147483647, 213 QMI_IPA_FILTER_ACTION_INVALID_V01 = 0, 214 QMI_IPA_FILTER_ACTION_SRC_NAT_V01 = 1, 215 QMI_IPA_FILTER_ACTION_DST_NAT_V01 = 2, 216 QMI_IPA_FILTER_ACTION_ROUTING_V01 = 3, 217 QMI_IPA_FILTER_ACTION_EXCEPTION_V01 = 4, 218 IPA_FILTER_ACTION_ENUM_MAX_ENUM_VAL_V01 = 2147483647 219 }; 220 221 struct ipa_filter_spec_type_v01 { 222 uint32_t filter_spec_identifier; 223 enum ipa_ip_type_enum_v01 ip_type; 224 struct ipa_filter_rule_type_v01 filter_rule; 225 enum ipa_filter_action_enum_v01 filter_action; 226 uint8_t is_routing_table_index_valid; 227 uint32_t route_table_index; 228 uint8_t is_mux_id_valid; 229 uint32_t mux_id; 230 }; 231 232 struct ipa_install_fltr_rule_req_msg_v01 { 233 uint8_t filter_spec_list_valid; 234 uint32_t filter_spec_list_len; 235 struct ipa_filter_spec_type_v01 filter_spec_list[QMI_IPA_MAX_FILTERS_V01]; 236 uint8_t source_pipe_index_valid; 237 uint32_t source_pipe_index; 238 uint8_t num_ipv4_filters_valid; 239 uint32_t num_ipv4_filters; 240 uint8_t num_ipv6_filters_valid; 241 uint32_t num_ipv6_filters; 242 uint8_t xlat_filter_indices_list_valid; 243 uint32_t xlat_filter_indices_list_len; 244 uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_V01]; 245 }; 246 247 struct ipa_filter_rule_identifier_to_handle_map_v01 { 248 uint32_t filter_spec_identifier; 249 uint32_t filter_handle; 250 }; 251 252 struct ipa_install_fltr_rule_resp_msg_v01 { 253 struct ipa_qmi_response_type_v01 resp; 254 uint8_t filter_handle_list_valid; 255 uint32_t filter_handle_list_len; 256 struct ipa_filter_rule_identifier_to_handle_map_v01 257 filter_handle_list[QMI_IPA_MAX_FILTERS_V01]; 258 }; 259 260 struct ipa_filter_handle_to_index_map_v01 { 261 uint32_t filter_handle; 262 uint32_t filter_index; 263 }; 264 265 struct ipa_fltr_installed_notif_req_msg_v01 { 266 uint32_t source_pipe_index; 267 enum ipa_qmi_result_type_v01 install_status; 268 uint32_t filter_index_list_len; 269 struct ipa_filter_handle_to_index_map_v01 270 filter_index_list[QMI_IPA_MAX_FILTERS_V01]; 271 272 uint8_t embedded_pipe_index_valid; 273 uint32_t embedded_pipe_index; 274 uint8_t retain_header_valid; 275 uint8_t retain_header; 276 uint8_t embedded_call_mux_id_valid; 277 uint32_t embedded_call_mux_id; 278 uint8_t num_ipv4_filters_valid; 279 uint32_t num_ipv4_filters; 280 uint8_t num_ipv6_filters_valid; 281 uint32_t num_ipv6_filters; 282 uint8_t start_ipv4_filter_idx_valid; 283 uint32_t start_ipv4_filter_idx; 284 uint8_t start_ipv6_filter_idx_valid; 285 uint32_t start_ipv6_filter_idx; 286 }; 287 288 struct ipa_fltr_installed_notif_resp_msg_v01 { 289 struct ipa_qmi_response_type_v01 resp; 290 }; 291 292 struct ipa_enable_force_clear_datapath_req_msg_v01 { 293 uint32_t source_pipe_bitmask; 294 uint32_t request_id; 295 uint8_t throttle_source_valid; 296 uint8_t throttle_source; 297 }; 298 299 struct ipa_enable_force_clear_datapath_resp_msg_v01 { 300 struct ipa_qmi_response_type_v01 resp; 301 }; 302 303 struct ipa_disable_force_clear_datapath_req_msg_v01 { 304 uint32_t request_id; 305 }; 306 307 struct ipa_disable_force_clear_datapath_resp_msg_v01 { 308 struct ipa_qmi_response_type_v01 resp; 309 }; 310 311 enum ipa_peripheral_speed_enum_v01 { 312 IPA_PERIPHERAL_SPEED_ENUM_MIN_ENUM_VAL_V01 = -2147483647, 313 QMI_IPA_PER_USB_FS_V01 = 1, 314 QMI_IPA_PER_USB_HS_V01 = 2, 315 QMI_IPA_PER_USB_SS_V01 = 3, 316 IPA_PERIPHERAL_SPEED_ENUM_MAX_ENUM_VAL_V01 = 2147483647 317 }; 318 319 enum ipa_pipe_mode_enum_v01 { 320 IPA_PIPE_MODE_ENUM_MIN_ENUM_VAL_V01 = -2147483647, 321 QMI_IPA_PIPE_MODE_HW_V01 = 1, 322 QMI_IPA_PIPE_MODE_SW_V01 = 2, 323 IPA_PIPE_MODE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 324 }; 325 326 enum ipa_peripheral_type_enum_v01 { 327 IPA_PERIPHERAL_TYPE_ENUM_MIN_ENUM_VAL_V01 = -2147483647, 328 QMI_IPA_PERIPHERAL_USB_V01 = 1, 329 QMI_IPA_PERIPHERAL_HSIC_V01 = 2, 330 QMI_IPA_PERIPHERAL_PCIE_V01 = 3, 331 IPA_PERIPHERAL_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 332 }; 333 334 struct ipa_config_req_msg_v01 { 335 uint8_t peripheral_type_valid; 336 enum ipa_peripheral_type_enum_v01 peripheral_type; 337 uint8_t hw_deaggr_supported_valid; 338 uint8_t hw_deaggr_supported; 339 uint8_t max_aggr_frame_size_valid; 340 uint32_t max_aggr_frame_size; 341 uint8_t ipa_ingress_pipe_mode_valid; 342 enum ipa_pipe_mode_enum_v01 ipa_ingress_pipe_mode; 343 uint8_t peripheral_speed_info_valid; 344 enum ipa_peripheral_speed_enum_v01 peripheral_speed_info; 345 uint8_t dl_accumulation_time_limit_valid; 346 uint32_t dl_accumulation_time_limit; 347 uint8_t dl_accumulation_pkt_limit_valid; 348 uint32_t dl_accumulation_pkt_limit; 349 uint8_t dl_accumulation_byte_limit_valid; 350 uint32_t dl_accumulation_byte_limit; 351 uint8_t ul_accumulation_time_limit_valid; 352 uint32_t ul_accumulation_time_limit; 353 uint8_t hw_control_flags_valid; 354 uint32_t hw_control_flags; 355 uint8_t ul_msi_event_threshold_valid; 356 uint32_t ul_msi_event_threshold; 357 uint8_t dl_msi_event_threshold_valid; 358 uint32_t dl_msi_event_threshold; 359 }; 360 361 struct ipa_config_resp_msg_v01 { 362 struct ipa_qmi_response_type_v01 resp; 363 }; 364 365 /*Service Message Definition*/ 366 #define QMI_IPA_INDICATION_REGISTER_REQ_V01 0x0020 367 #define QMI_IPA_INDICATION_REGISTER_RESP_V01 0x0020 368 #define QMI_IPA_INIT_MODEM_DRIVER_REQ_V01 0x0021 369 #define QMI_IPA_INIT_MODEM_DRIVER_RESP_V01 0x0021 370 #define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_V01 0x0022 371 #define QMI_IPA_INSTALL_FILTER_RULE_REQ_V01 0x0023 372 #define QMI_IPA_INSTALL_FILTER_RULE_RESP_V01 0x0023 373 #define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_V01 0x0024 374 #define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_V01 0x0024 375 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0025 376 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0025 377 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0026 378 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0026 379 #define QMI_IPA_CONFIG_REQ_V01 0x0027 380 #define QMI_IPA_CONFIG_RESP_V01 0x0027 381 382 /* add for max length*/ 383 #define QMI_IPA_INIT_MODEM_DRIVER_REQ_MAX_MSG_LEN_V01 98 384 #define QMI_IPA_INIT_MODEM_DRIVER_RESP_MAX_MSG_LEN_V01 21 385 #define QMI_IPA_INDICATION_REGISTER_REQ_MAX_MSG_LEN_V01 4 386 #define QMI_IPA_INDICATION_REGISTER_RESP_MAX_MSG_LEN_V01 7 387 #define QMI_IPA_INSTALL_FILTER_RULE_REQ_MAX_MSG_LEN_V01 11293 388 #define QMI_IPA_INSTALL_FILTER_RULE_RESP_MAX_MSG_LEN_V01 523 389 #define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_MAX_MSG_LEN_V01 574 390 #define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_MAX_MSG_LEN_V01 7 391 #define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_MAX_MSG_LEN_V01 7 392 393 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 18 394 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 7 395 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 396 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 397 398 #define QMI_IPA_CONFIG_REQ_MAX_MSG_LEN_V01 81 399 #define QMI_IPA_CONFIG_RESP_MAX_MSG_LEN_V01 7 400 /* Service Object Accessor */ 401 402 #endif /* IPA_QMI_SERVICE_V01_H */ 403 404 #ifndef _UAPI_MSM_IPC_H_ 405 #define _UAPI_MSM_IPC_H_ 406 407 #include <linux/ioctl.h> 408 #include <linux/types.h> 409 410 struct msm_ipc_port_addr { 411 uint32_t node_id; 412 uint32_t port_id; 413 }; 414 415 struct msm_ipc_port_name { 416 uint32_t service; 417 uint32_t instance; 418 }; 419 420 struct msm_ipc_addr { 421 unsigned char addrtype; 422 union { 423 struct msm_ipc_port_addr port_addr; 424 struct msm_ipc_port_name port_name; 425 } addr; 426 }; 427 428 #define MSM_IPC_WAIT_FOREVER (~0) /* timeout for permanent subscription */ 429 430 #ifndef AF_MSM_IPC 431 #define AF_MSM_IPC 27 432 #endif 433 434 #ifndef PF_MSM_IPC 435 #define PF_MSM_IPC AF_MSM_IPC 436 #endif 437 438 #define MSM_IPC_ADDR_NAME 1 439 #define MSM_IPC_ADDR_ID 2 440 441 struct sockaddr_msm_ipc { 442 unsigned short family; 443 struct msm_ipc_addr address; 444 unsigned char reserved; 445 }; 446 447 struct config_sec_rules_args { 448 int num_group_info; 449 uint32_t service_id; 450 uint32_t instance_id; 451 unsigned reserved; 452 gid_t group_id[0]; 453 }; 454 455 #define IPC_ROUTER_IOCTL_MAGIC (0xC3) 456 457 #define IPC_ROUTER_IOCTL_GET_VERSION \ 458 _IOR(IPC_ROUTER_IOCTL_MAGIC, 0, unsigned int) 459 460 #define IPC_ROUTER_IOCTL_GET_MTU _IOR(IPC_ROUTER_IOCTL_MAGIC, 1, unsigned int) 461 462 #define IPC_ROUTER_IOCTL_LOOKUP_SERVER \ 463 _IOWR(IPC_ROUTER_IOCTL_MAGIC, 2, struct sockaddr_msm_ipc) 464 465 #define IPC_ROUTER_IOCTL_GET_CURR_PKT_SIZE \ 466 _IOR(IPC_ROUTER_IOCTL_MAGIC, 3, unsigned int) 467 468 #define IPC_ROUTER_IOCTL_BIND_CONTROL_PORT \ 469 _IOR(IPC_ROUTER_IOCTL_MAGIC, 4, unsigned int) 470 471 #define IPC_ROUTER_IOCTL_CONFIG_SEC_RULES \ 472 _IOR(IPC_ROUTER_IOCTL_MAGIC, 5, struct config_sec_rules_args) 473 474 struct msm_ipc_server_info { 475 uint32_t node_id; 476 uint32_t port_id; 477 uint32_t service; 478 uint32_t instance; 479 }; 480 481 struct server_lookup_args { 482 struct msm_ipc_port_name port_name; 483 int num_entries_in_array; 484 int num_entries_found; 485 uint32_t lookup_mask; 486 struct msm_ipc_server_info srv_info[0]; 487 }; 488 489 #endif 490 491 #ifndef _UAPI_MSM_RMNET_H_ 492 #define _UAPI_MSM_RMNET_H_ 493 494 /* Bitmap macros for RmNET driver operation mode. */ 495 #define RMNET_MODE_NONE (0x00) 496 #define RMNET_MODE_LLP_ETH (0x01) 497 #define RMNET_MODE_LLP_IP (0x02) 498 #define RMNET_MODE_QOS (0x04) 499 #define RMNET_MODE_MASK \ 500 (RMNET_MODE_LLP_ETH | RMNET_MODE_LLP_IP | RMNET_MODE_QOS) 501 502 #define RMNET_IS_MODE_QOS(mode) ((mode & RMNET_MODE_QOS) == RMNET_MODE_QOS) 503 #define RMNET_IS_MODE_IP(mode) ((mode & RMNET_MODE_LLP_IP) == RMNET_MODE_LLP_IP) 504 505 enum rmnet_ioctl_cmds_e { 506 RMNET_IOCTL_SET_LLP_ETHERNET = 0x000089F1, /* Set Ethernet protocol */ 507 RMNET_IOCTL_SET_LLP_IP = 0x000089F2, /* Set RAWIP protocol */ 508 RMNET_IOCTL_GET_LLP = 0x000089F3, /* Get link protocol */ 509 RMNET_IOCTL_SET_QOS_ENABLE = 0x000089F4, /* Set QoS header enabled */ 510 RMNET_IOCTL_SET_QOS_DISABLE = 0x000089F5, /* Set QoS header disabled*/ 511 RMNET_IOCTL_GET_QOS = 0x000089F6, /* Get QoS header state */ 512 RMNET_IOCTL_GET_OPMODE = 0x000089F7, /* Get operation mode */ 513 RMNET_IOCTL_OPEN = 0x000089F8, /* Open transport port */ 514 RMNET_IOCTL_CLOSE = 0x000089F9, /* Close transport port */ 515 RMNET_IOCTL_FLOW_ENABLE = 0x000089FA, /* Flow enable */ 516 RMNET_IOCTL_FLOW_DISABLE = 0x000089FB, /* Flow disable */ 517 RMNET_IOCTL_FLOW_SET_HNDL = 0x000089FC, /* Set flow handle */ 518 RMNET_IOCTL_EXTENDED = 0x000089FD, /* Extended IOCTLs */ 519 RMNET_IOCTL_MAX 520 }; 521 522 enum rmnet_ioctl_extended_cmds_e { 523 /* RmNet Data Required IOCTLs */ 524 RMNET_IOCTL_GET_SUPPORTED_FEATURES = 0x0000, /* Get features */ 525 RMNET_IOCTL_SET_MRU = 0x0001, /* Set MRU */ 526 RMNET_IOCTL_GET_MRU = 0x0002, /* Get MRU */ 527 RMNET_IOCTL_GET_EPID = 0x0003, /* Get endpoint ID */ 528 RMNET_IOCTL_GET_DRIVER_NAME = 0x0004, /* Get driver name */ 529 RMNET_IOCTL_ADD_MUX_CHANNEL = 0x0005, /* Add MUX ID */ 530 RMNET_IOCTL_SET_EGRESS_DATA_FORMAT = 0x0006, /* Set EDF */ 531 RMNET_IOCTL_SET_INGRESS_DATA_FORMAT = 0x0007, /* Set IDF */ 532 RMNET_IOCTL_SET_AGGREGATION_COUNT = 0x0008, /* Set agg count */ 533 RMNET_IOCTL_GET_AGGREGATION_COUNT = 0x0009, /* Get agg count */ 534 RMNET_IOCTL_SET_AGGREGATION_SIZE = 0x000A, /* Set agg size */ 535 RMNET_IOCTL_GET_AGGREGATION_SIZE = 0x000B, /* Get agg size */ 536 RMNET_IOCTL_FLOW_CONTROL = 0x000C, /* Do flow control */ 537 RMNET_IOCTL_GET_DFLT_CONTROL_CHANNEL = 0x000D, /* For legacy use */ 538 RMNET_IOCTL_GET_HWSW_MAP = 0x000E, /* Get HW/SW map */ 539 RMNET_IOCTL_SET_RX_HEADROOM = 0x000F, /* RX Headroom */ 540 RMNET_IOCTL_GET_EP_PAIR = 0x0010, /* Endpoint pair */ 541 RMNET_IOCTL_SET_QOS_VERSION = 0x0011, /* 8/6 byte QoS hdr*/ 542 RMNET_IOCTL_GET_QOS_VERSION = 0x0012, /* 8/6 byte QoS hdr*/ 543 RMNET_IOCTL_GET_SUPPORTED_QOS_MODES = 0x0013, /* Get QoS modes */ 544 RMNET_IOCTL_SET_SLEEP_STATE = 0x0014, /* Set sleep state */ 545 RMNET_IOCTL_SET_XLAT_DEV_INFO = 0x0015, /* xlat dev name */ 546 RMNET_IOCTL_EXTENDED_MAX = 0x0016 547 }; 548 549 /* Return values for the RMNET_IOCTL_GET_SUPPORTED_FEATURES IOCTL */ 550 #define RMNET_IOCTL_FEAT_NOTIFY_MUX_CHANNEL (1 << 0) 551 #define RMNET_IOCTL_FEAT_SET_EGRESS_DATA_FORMAT (1 << 1) 552 #define RMNET_IOCTL_FEAT_SET_INGRESS_DATA_FORMAT (1 << 2) 553 #define RMNET_IOCTL_FEAT_SET_AGGREGATION_COUNT (1 << 3) 554 #define RMNET_IOCTL_FEAT_GET_AGGREGATION_COUNT (1 << 4) 555 #define RMNET_IOCTL_FEAT_SET_AGGREGATION_SIZE (1 << 5) 556 #define RMNET_IOCTL_FEAT_GET_AGGREGATION_SIZE (1 << 6) 557 #define RMNET_IOCTL_FEAT_FLOW_CONTROL (1 << 7) 558 #define RMNET_IOCTL_FEAT_GET_DFLT_CONTROL_CHANNEL (1 << 8) 559 #define RMNET_IOCTL_FEAT_GET_HWSW_MAP (1 << 9) 560 561 /* Input values for the RMNET_IOCTL_SET_EGRESS_DATA_FORMAT IOCTL */ 562 #define RMNET_IOCTL_EGRESS_FORMAT_MAP (1 << 1) 563 #define RMNET_IOCTL_EGRESS_FORMAT_AGGREGATION (1 << 2) 564 #define RMNET_IOCTL_EGRESS_FORMAT_MUXING (1 << 3) 565 #define RMNET_IOCTL_EGRESS_FORMAT_CHECKSUM (1 << 4) 566 567 /* Input values for the RMNET_IOCTL_SET_INGRESS_DATA_FORMAT IOCTL */ 568 #define RMNET_IOCTL_INGRESS_FORMAT_MAP (1 << 1) 569 #define RMNET_IOCTL_INGRESS_FORMAT_DEAGGREGATION (1 << 2) 570 #define RMNET_IOCTL_INGRESS_FORMAT_DEMUXING (1 << 3) 571 #define RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM (1 << 4) 572 573 /* User space may not have this defined. */ 574 #ifndef IFNAMSIZ 575 #define IFNAMSIZ 16 576 #endif 577 578 struct rmnet_ioctl_extended_s { 579 uint32_t extended_ioctl; 580 union { 581 uint32_t data; /* Generic data field for most extended IOCTLs */ 582 int8_t if_name[IFNAMSIZ]; 583 struct { 584 uint32_t mux_id; 585 int8_t vchannel_name[IFNAMSIZ]; 586 } rmnet_mux_val; 587 struct { 588 uint8_t flow_mode; 589 uint8_t mux_id; 590 } flow_control_prop; 591 struct { 592 uint32_t consumer_pipe_num; 593 uint32_t producer_pipe_num; 594 } ipa_ep_pair; 595 } u; 596 }; 597 598 struct rmnet_ioctl_data_s { 599 union { 600 uint32_t operation_mode; 601 uint32_t tcm_handle; 602 } u; 603 }; 604 605 #define RMNET_IOCTL_QOS_MODE_6 (1 << 0) 606 #define RMNET_IOCTL_QOS_MODE_8 (1 << 1) 607 608 #define QMI_QOS_HDR_S __attribute((__packed__)) qmi_qos_hdr_s 609 struct QMI_QOS_HDR_S { 610 unsigned char version; 611 unsigned char flags; 612 uint32_t flow_id; 613 }; 614 615 struct qmi_qos_hdr8_s { 616 struct QMI_QOS_HDR_S hdr; 617 uint8_t reserved[2]; 618 } __attribute((__packed__)); 619 620 #endif 621
